pi6c2509-133 Pericom Semiconductor Corporation, pi6c2509-133 Datasheet
pi6c2509-133
Manufacturer Part Number
pi6c2509-133
Description
3.3v, Low-noise Phase-locked Loop Clock Driver With 9 Clock Outputs
Manufacturer
Pericom Semiconductor Corporation
Datasheet
1.PI6C2509-133.pdf
(5 pages)
Available stocks
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Price
Part Number:
pi6c2509-133L
Manufacturer:
PERICOM
Quantity:
20 000
Company:
Part Number:
pi6c2509-133LE
Manufacturer:
PER
Quantity:
1 116
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Features
• Operating Frequency up to 150 MHz
• Low-Noise Phase-Locked Loop Clock Distribution to meet
• Allows Clock Input to have Spread Spectrum modulation
• Zero input-to-output delay: Distribute One Clock Input to
• Low jitter: cycle-to-cycle jitter ±75ps max.
• 30-ohm on-chip series damping resistor at clock output drivers
• Operates at 3.3V V
• Package (Pb-free and Green available):
Logic Block Diagram
133 MHz Registered DIMM Synchronous DRAM module
specifications for server/workstation/PC applications
for EMI reduction
one bank of five and one bank of four outputs, with
separate output enables
for low noise and EMI reduction
- 24-pin TSSOP (L)
CLK_IN
FB_IN
AV CC
1G
2G
CC
PLL
5
4
1Y[0:4]
2Y[0:3]
FB_OUT
1
Description
The PI6C2509-133 is a “quiet,” low-skew, low-jitter, phase-locked
loop (PLL) clock driver, distributing low-noise clock signals for
SDRAM and server applications. By connecting the feedback
FB_OUT output to the feedback FB_IN input, the propagation
delay from the CLK_IN input to any clock output will be nearly zero.
This zero-delay feature allows the CLK_IN input clock to be
distributed, providing 5 clocks for the first bank, and an additional
4 clocks for the second bank.
This clock driver is designed to meet the PC133 SDRAM Registered
DIMM specification. For test purposes, the PLL can be bypassed
by strapping AV
Product Pin Configuration
FB_OUT
AGND
Clock Driver with 9 Clock Outputs
GND
GND
V CC
V CC
1Y0
1Y1
1Y2
1Y3
1Y4
1G
CC
Low-Noise Phase-Locked Loop
to ground.
1
2
3
4
5
6
7
8
9
10
11
12
24-Pin
L
24
23
22
21
20
19
18
17
16
15
14
13
PI6C2509-133
CLK_IN
AV CC
V CC
2Y0
2Y1
GND
GND
2Y2
2Y3
V CC
2G
FB_IN
PS8544C
07/19/05
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pi6c2509-133 Summary of contents
Page 1
... FB_IN AV CC Clock Driver with 9 Clock Outputs Description The PI6C2509-133 is a “quiet,” low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing low-noise clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. ...
Page 2
... PI6C2509-133 Low-Noise, Phase-Locked Loop Clock Driver with 9 Clock Outputs ...
Page 3
... – – – PI6C2509-133 ° μ º ...
Page 4
... T = –40~85° 15pF – – PI6C2509-133 PS8544C 07/19/05 ...
Page 5
... Max SEATING PLANE .002 0.05 .006 0.15 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS PI6C2509-133 Low-Noise, Phase-Locked Loop Clock Driver with 9 Clock Outputs 0.09 .004 0.20 .008 0.45 .018 0.75 .030 .252 BSC 6 ...