pi6c39911 Pericom Semiconductor Corporation, pi6c39911 Datasheet - Page 10

• Manufacturer Part Number: pi6c39911
• Description: 3.3v, Programmable Skew Pll Clock Driver With 750ps Accuracy, Lvttl, 3.75 To 110 Mhz
• Manufacturer: Pericom Semiconductor Corporation

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Figure 8 shows the PI6C39911 connected in series to construct a zero
skew clock distribution tree between boards. Delays of the down
stream clock buffers can be programmed to compensate for the wire
length (i.e., select negative skew equal to the wire delay) necessary
to connect them to the master clock source, approximating a zero-
06-0248
System
Clock
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
Figure 8. Board-to-Board Clock Distribution
REF
1 0
L3
delay clock tree. Cascaded clock buffers will accumulate low
frequency jitter because of the non-ideal filtering characteristics of
the PLL filter. It is recommended that not more than two clock buffers
be connected in series.
L4
L1
L2
Programmable Skew Clock Buffer - SuperClock
Z
0
3.3V High Speed LVTTL or Balanced Output
Z
Z
Z
0
0
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
0
LOAD
LOAD
LOAD
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
LOAD
PS8497F
PI6C39911
08/28/06
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