cy7c1386b-cy7c1387b Cypress Semiconductor Corporation., cy7c1386b-cy7c1387b Datasheet - Page 6

• Manufacturer Part Number: cy7c1386b-cy7c1387b
• Description: 512k X 36/1m X 18 Pipelined Dcd Sram
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-05195 Rev. **
Pin Definitions
DQa, DPa
DQb, DPb
DQd, DPd
DQc, DPc
MODE
Name
ADSP
ADSC
BWE
BWa
BWb
BWc
BWd
CLK
ADV
CE
CE
CE
GW
OE
A0
A1
ZZ
A
1
2
3
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-Clock
Input-Pin
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
I/O-
I/O
Address Inputs used to select one of the address locations. Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE
and CE
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable input, active LOW. When asserted LOW on the rising
edge of CLK, a global Write is conducted (ALL bytes are written, regardless
of the values on BW
Byte Write Enable input, active LOW. Sampled on the rising edge of CLK.
This signal must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW during a burst
operation.
Chip Enable 1 input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE
ignored if CE
Chip Enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE
Chip Enable 3 input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE
Output Enable, asynchronous input, active LOW. Controls the direction of
the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the first clock of a read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted,
it automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK.
When asserted LOW, A is captured in the address registers. A
loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE
Address Strobe from Controller, sampled on the rising edge of CLK.
When asserted LOW, A
loaded into the burst counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
Selects Burst Order. When tied to GND selects linear burst sequence. When
tied to V
pin and should remain static during device operation.
ZZ “sleep” input. This active HIGH input places the device in a non-time
critical “sleep” condition with data integrity preserved.
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A
rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are
placed in a three-state condition.DQ a,b,c and d are 8 bits wide. DP a,b,c and
d are 1 bit wide.
3
DDQ
are sampled active. A
or left floating selects interleaved burst sequence. This is a strap
1
is HIGH.
a,b,c,d
2
1
1
[x:0]
and CE
and CE
and CE
and BWE).
is captured in the address registers. A
[1:0]
2
3
3
Description
to select/deselect the device (TQFP only).
to select/deselect the device. ADSP is
to select/deselect the device (TQFP only).
feeds the 2-bit counter.
1
X
is deasserted HIGH.
during the previous clock
CY7C1386B
CY7C1387B
[1:0]
[1:0]
Page 6 of 32
are also
1,
are also
CE
2
,