ad7886kp Analog Devices, Inc., ad7886kp Datasheet - Page 11

• Manufacturer Part Number: ad7886kp
• Description: Lc2mos 12-bit, 750 Khz/1 Mhz, Sampling Adc
• Manufacturer: Analog Devices, Inc.

REV. B
DSP56000
TMS320C25
ADSP-2100
OUT
CLK
Figure 18. AD7886–TMS320C25 Interface
Figure 17. AD7886–ADSP-2100 Interface
A15
D23
Figure 19. AD7886–DSP56000 Interface
IRQ
X/Y
READY
RD
DMACK
A0
DS
D0
DMA13
DMD15
STRB
DMRD
DMA0
DMD0
DMS
MSC
IRQn
R/W
D15
A15
INT
A0
D0
IS
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
EN1
EN2
ADDRESS BUS
ADDRESS BUS
DATA BUS
ENCODE
EN
ADDRESS BUS
EN
ADDR
ENCODE
G2
ENCODE
DATA BUS
ADDR
ADDR
DATA BUS
Q
74HC74
Q11
Q0
OE
74HC374
CLR
2X
CLK
CLK
D11
D0
D
+
5V
CS
RD
BUSY
DB11
DB0
AD7886*
RD
DB11
CS
BUSY
DB0
AD7886*
AD7886*
CS
BUSY
RD
DB11
DB0
CONVST
CONVST
TIMER
TIMER
CONVST
TIMER
–11–
AD7886–MC68000
Applications requiring conversions to be initiated by the micro-
processor rather than an external timer may decode a CONVST
signal from the address bus. An example is given in Figure 20
with the MC68000 processor. A write instruction starts conver-
sion while a read instruction reads the data when conversion is
complete. A delay at least as long as the ADC conversion time
must be allowed between initiating a conversion and reading the
ADC data into the processor. In Figure 20, BUSY is used to
drive the processor into a WAIT state if the processor attempts
to read data before conversion is complete.
Conversion is initiated with a write instruction to the ADC:
Move.W D0,ADC
Data is transferred to the processor with a read instruction;
BUSY will force the processor to WAIT for the end of conver-
sion if a conversion is in progress.
Move.W ADC,DO
AD7886–Z-80/8085A
For 8-bit processors, an external latch is required to store four
bits of the conversion result (4 LSBs in Figure 21). The data is
then read in two bytes: one read from the ADC and a second
from the latch.
Figure 21 shows a typical interface suitable for the Z-80 or the
8085A. Not shown in the Figure is the 8-bit latch needed to
demultiplex the 8085A common address/data bus. The follow-
ing LOAD instruction reads the conversion result into the HL
register pair:
For the 8085A–LHLD
For the Z-80–LDHL
This is a two byte read instruction. The first byte to be read has
to be the high byte (DB11 to DB4). At the end of the first read
operation, the rising edge of CS and RD clocks the 4 LSBs into
74HC374 latches. The second byte (4 LSBs) is then read from
these latches.
MC68000
DTACK
Figure 20. AD7886–MC68000 Interface
R/W
A15
D11
A0
AS
D0
*ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS BUS
EN
ENCODE
ADDR
(ADC) (ADC = ADC address)
(ADC) (ADC = ADC address)
DATA BUS
(ADC = ADC address)
(ADC = ADC address)
AD7886
CS
CONVST
RD
BUSY
DB0
DB11
AD7886*