ad725-eb Analog Devices, Inc., ad725-eb Datasheet - Page 4

• Manufacturer Part Number: ad725-eb
• Description: Low Cost Rgb To Ntsc/pal Encoder With Luma Trap Port
• Manufacturer: Analog Devices, Inc.

AD725
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
*The Luminance, Chrominance and Composite Outputs are at twice normal levels for driving 75
Mnemonic
STND
AGND
4FSC
APOS
CE
RIN
GIN
BIN
CRMA
COMP
LUMA
YTRAP
DGND
DPOS
VSYNC
HSYNC
15
16
1
5
3
Circuit A
DGND
DPOS
4FSC Clock Input.
Horizontal Sync Signal (or CSYNC signal). TTL Logic Levels.
Description
Encoding Standard Pin. A Logic HIGH input selects NTSC encoding.
A Logic LOW input selects PAL encoding.
TTL Logic Levels.
Analog Ground Connection.
For NTSC: 14.318 180 MHz.
For PAL: 17.734 475 MHz.
TTL Logic Levels.
Analog Positive Supply (+5 V
Chip Enable. A Logic HIGH input enables the encode function.
A Logic LOW input powers down chip when not in use.
TTL Logic Levels.
Red Component Video Input.
0 mV to 714 mV AC-Coupled.
Green Component Video Input.
0 mV to 714 mV AC-Coupled.
Blue Component Video Input.
0 mV to 714 mV AC-Coupled.
Chrominance Output.*
Approximately 1.8 V peak-to-peak for both NTSC and PAL.
Composite Video Output.*
Approximately 2.5 V peak-to-peak for both NTSC and PAL.
Luminance plus CSYNC Output.*
Approximately 2 V peak-to-peak for both NTSC and PAL.
Luminance Trap Filter Tap. Attach L-C resonant network to reduce cross-color artifacts. Circuit D
Digital Ground Connection.
Digital Positive Supply (+5 V
Vertical Sync Signal (if using external CSYNC set at > +2 V). TTL Logic Levels.
6
7
8
DGND
DPOS
Circuit B
Figure 1. Equivalent Circuits
5%).
5%).
V
PIN DESCRIPTIONS
CLAMP
–4–
AGND
APOS
Circuit C
reverse-terminated lines.
DGND
DPOS
10
11
9
APOS
AGND
1k
Circuit D
Equivalent Circuit
Circuit A
Circuit A
Circuit A
Circuit B
Circuit B
Circuit B
Circuit C
Circuit C
Circuit C
Circuit A
Circuit A
DPOS
DGND
12
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