mt4lc4m4e8tg-6-s Micron Semiconductor Products, mt4lc4m4e8tg-6-s Datasheet - Page 9

• Manufacturer Part Number: mt4lc4m4e8tg-6-s
• Description: 16mb Edo Mt4lc4m4e8dj-5
• Manufacturer: Micron Semiconductor Products

NOTES
1. All voltages referenced to V
2. The minimum specifications are used only to indicate
3. An initial pause of 100µs is required after power-up,
4. NC pins are assumed to be left floating and are not
5. I
6. Column address changed once each cycle.
7. Enables on-chip refresh and address counters.
8. This parameter is sampled. V
9. AC characteristics assume
10. V
11. In addition to meeting the transition rate specifica-
12. Measured with a load equivalent to two TTL gates
13.
14. Requires that
15. If CAS# is LOW at the falling edge of RAS#, Q will be
16. These parameters are referenced to CAS# leading
4 Meg x 4 EDO DRAM
D47.p65 – Rev. 6/98
cycle time at which proper operation over the full
temperature range (0˚C ≤ T
followed by eight RAS# refresh cycles (RAS#-ONLY
or CBR with WE# HIGH), before proper device
operation is ensured. The eight RAS# cycle wake-ups
should be repeated any time the
requirement is exceeded.
tested for leakage.
Specified values are obtained with minimum cycle
time and the outputs open.
measuring timing of input signals. Transition times
are measured between V
and V
tion, all input signals must transit between V
V
and 100pF; and V
t
operating parameters.
WRITE cycles.
READ-MODIFY-WRITE cycles. If
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If
t
t
and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. OE# held HIGH
and WE# taken LOW after CAS# goes LOW results in
a LATE WRITE (OE#-controlled) cycle.
t
WRITE cycle.
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS# must be
pulsed HIGH for
edge in EARLY WRITE cycles and WE# leading edge
in LATE WRITE or READ-MODIFY-WRITE cycles.
WCS,
RWD (MIN),
CWD (MIN), the cycle is a READ-MODIFY-WRITE
CWD and
CC
IH
IL
is dependent on output loading and cycle rates.
(or between V
(MIN) and V
IH
t
RWD,
).
t
AWD are not applicable in a LATE
t
t
t
AA and
AWD and
AWD ≥
t
RWD,
IL
OL
t
IL
t
CP.
WCS <
(MAX) are reference levels for
and V
= 0.8V and V
t
t
AWD and
t
t
WCS applies to EARLY
AWD (MIN) and
RAC are not violated.
IH
t
IH
CWD are not restrictive
t
t
WCS (MIN) and
A
and V
T = 2.5ns.
) in a monotonic manner.
SS
≤ 70˚C) is ensured.
DD
.
= +3.3V; f = 1 MHz.
t
IL
REF refresh
OH
t
CWD apply to
t
WCS ≥
(or between V
= 2V.
t
WCS,
t
CWD ≥
t
WCS
t
RWD ≥
IH
t
RWD,
and
IL
9
17. If OE# is tied permanently LOW, LATE WRITE or
18. LATE WRITE and READ-MODIFY-WRITE cycles
19. Requires that
20.
21. The
22. The
23. Either
24. A HIDDEN REFRESH may also be performed after
25.
26. V
READ-MODIFY-WRITE operations are not permis-
sible and should not be attempted. Additionally, WE#
must be pulsed during CAS# HIGH time in order to
place I/O buffers in High-Z.
must have both
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE cycle.
The DQs will provide the previously read data if
CAS# remains LOW and OE# is taken back LOW
after
going back LOW, the DQs will remain open.
t
achieves the open circuit condition and is not
referenced to V
rising edge of RAS# or CAS#, whichever occurs last.
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively by
t
without the
must always be met.
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively by
t
without the
be met.
cycle.
a WRITE cycle. In this case, WE# is LOW and
OE# is HIGH.
The refresh period is extended from 32ms (2K refresh)
or 64ms (4K refresh) to 128ms (both 2K and 4K
refresh). For 4K refresh,
rows = 31.25µs) and for 2K refresh,
(128ms/2,048 rows = 62.5µs).
width ≤ 10ns, and the pulse width cannot be greater
than one third of the cycle rate. V
(MIN) = -2V for a pulse width ≤ 10ns, and the pulse
width cannot be greater than one third of the cycle
rate.
OFF (MAX) defines the time at which the output
RAD was greater than the specified
AA (
RCD was greater than the specified
CAC (
IH
overshoot: V
t
t
RAD (MAX) limit is no longer specified.
RCD (MAX) limit is no longer specified.
t
t
OEH is met. If CAS# goes HIGH prior to OE#
RAC and
t
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RCH or
RAC [MIN] no longer applied). With or
t
t
RAD (MAX) limit,
RCD limit,
t
AA and
OH
t
t
t
RRH must be satisfied for a READ
CAC no longer applied). With or
OD and
IH
or V
(MAX) = V
OL
t
CAC are not violated.
t
t
AA and
RC = 31.25µs (128ms/4,096
. It is referenced from the
t
OEH met (OE# HIGH
DD
t
AA,
t
EDO DRAM
+ 2V for a pulse
IL
CAC must always
undershoot: V
4 MEG x 4
t
RC = 62.5µs
t
t
t
RCD (MAX)
RAD (MAX)
RAC and
1998, Micron Technology, Inc.
t
t
RCD
RAD
t
CAC
IL