pi7c8154a Pericom Semiconductor Corporation, pi7c8154a Datasheet - Page 29

• Manufacturer Part Number: pi7c8154a
• Description: 2-port Pci-to-pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

2.7.4
2.7.5
Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB address
boundary, or until the initiator de-asserts FRAME#. Section 2.7.6 describes flow-through mode
during read operations.
Table 2-4 shows the read pre-fetch address boundaries for read transactions during non-flow-
through mode.
Table 2-4 READ PREFETCH ADDRESS BOUNDARIES
- does not matter if it is prefetchable or non-prefetchable
* don’t care
Table 2-5 READ TRANSACTION PREFETCHING
See Section 3.3 for detailed information about prefetchable and non-prefetchable address spaces.
DELAYED READ REQUESTS
PI7C8154A treats all read transactions as delayed read transactions, which means that the read
request from the initiator is posted into a delayed transaction queue. Read data from the target is
placed in the read data queue directed toward the initiator bus interface and is transferred to the
initiator when the initiator repeats the read transaction.
PI7C8154A accepts a delayed read request, by sampling the read address, read bus command, and
address parity. When IRDY# is asserted, PI7C8154A then samples the byte enable bits for the first
data phase. This information is entered into the delayed transaction queue. PI7C8154A terminates
the transaction by signaling a target retry to the initiator. Upon reception of the target retry, the
initiator is required to continue to repeat the same read transaction until at least one data transfer is
completed, or until a target response (target abort or master abort) other than a target retry is
received.
DELAYED READ COMPLETION ON TARGET BUS
When delayed read request reaches the head of the delayed transaction queue, PI7C8154A
arbitrates for the target bus and initiates the read transaction only if all previously queued posted
write transactions have been delivered. PI7C8154A uses the exact read address and read command
Type of Transaction
Configuration Read
I/O Read
Memory Read
Memory Read
Memory Read
Memory Read Line
Memory Read Line
Memory Read Multiple
Memory Read Multiple
Type of Transaction
I/O Read
Configuration Read
Memory Read
Memory Read Line
Memory Read Multiple
Address Space
-
-
Non-Prefetchable
Prefetchable
Prefetchable
-
-
-
-
Read Behavior
Prefetching never allowed
Prefetching never allowed
Downstream: Prefetching used if address is prefetchable space
Upstream: Prefetching used or programmable
Prefetching always used
Prefetching always used
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Cache Line Size
(CLS)
CLS = 0 or 16
*
*
*
CLS = 0 or 16
CLS = 1, 2, 4, 8
CLS = 0 or 16
CLS = 1, 2, 4, 8
CLS = 1, 2, 4, 8
Prefetch Aligned Address Boundary
One DWORD (no prefetch)
One DWORD (no prefetch)
One DWORD (no prefetch)
16-DWORD aligned address boundary
Cache line address boundary
16-DWORD aligned address boundary
Cache line boundary
Queue full
Second cache line boundary
ASYNCHRONOUS 2-PORT
JULY 2004 REVISION 1.00
PCI-to-PCI BRIDGE
Advance Information
PI7C8154A