ics84330c Integrated Device Technology, ics84330c Datasheet - Page 3

• Manufacturer Part Number: ics84330c
• Description: 700mhz, Low Jitter, Crystal-to-3.3v Differential Lvpecl Frequency Synthesizer
• Manufacturer: Integrated Device Technology

Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
Symbol
C
R
R
ICS84330C
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
IN
PULLUP
PULLDOWN
XTAL1, XTAL2
nFOUT, FOUT
M0, M1, M2
M3, M4, M5
FREF_EXT
M6, M7, M8
XTAL_SEL
S_CLOCK
nP_LOAD
S_LOAD
S_DATA
N0, N1
Name
TEST
V
V
V
OE
CCA
nc
CC
EE
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Unused
Output
Output
Power
Power
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pullup
Pullup
Description
Analog supply pin.
Crystal oscillator interface. XTAL1 is an oscillator input, XTAL2 is an oscillator output.
Selects between the crystal oscillator or FREF_EXT inputs as the PLL reference
source. Selects XTAL inputs when HIGH. Selects FREF_EXT when LOW.
LVCMOS / LVTTL interface levels.
Output enable. LVCMOS / LVTTL interface levels.
Parallel load input. Determines when data present at M8:M0 is loaded into M divider,
and when data present at N1:N0 sets the N output divide value.
LVCMOS / LVTTL interface levels.
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
LVCMOS / LVTTL interface levels.
Determines N output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
Negative supply pins.
Test output which is used in the serial mode of operation.
Single-ended LVPECL interface levels.
Core supply pins.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
No connect.
PLL reference input. LVCMOS / LVTTL interface levels.
Clocks the serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the M divider.
LVCMOS / LVTTL interface levels.
Test Conditions
3
Minimum
Typical
ICS84330CV REV. C JANUARY 28, 2009
51
51
4
Maximum
Units
k
k
pF
Ω
Ω