ics841s04 Integrated Device Technology, ics841s04 Datasheet - Page 3

• Manufacturer Part Number: ics841s04
• Description: Programmable Low-jitter Xtal Or Lvcmos-input Hcsl-output 4-output 100-mhz Clock Synthesizer
• Manufacturer: Integrated Device Technology

S
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock
output buffers, can be individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting upon power-up, and therefore, use of this
interface is optional. Clock device register changes are nor-
mally made upon system initialization, if any are required. The
interface cannot be used during system operation for power
management functions.
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The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in se-
quential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the sys-
tem controller can access individually indexed bytes. The off-
set of the indexed byte is encoded in the command code, as
described in Table 3A.
The block write and block read protocol is outlined in Table 3B,
while Table 3C outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
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ICS841S04BGI REV. C MAY 23, 2007
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