ics8535ag-21t Integrated Device Technology, ics8535ag-21t Datasheet - Page 10

• Manufacturer Part Number: ics8535ag-21t
• Description: Low Skew, 1-to-4 Lvcmos-to-3.3v Lvpecl Fanout Buffer
• Manufacturer: Integrated Device Technology

This section provides information on power dissipation and junction temperature for the ICS8535BI-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8535BI-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 91.1°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are loaded, supply
voltage, air flow, and the type of board (single layer or multi-layer).
T
IDT
T
ABLE
ABLE
ICS8535BI-01
LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
™
/ ICS
6A. T
6B.
Power (core)
Power (outputs)
If all outputs are loaded, the total power is 4 x 30mW = 120mW
Total Power
The equation for Tj is as follows: Tj =
Tj = Junction Temperature
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
85°C + 0.276W * 91.1°C/W = 110.1°C. This is well below the limit of 125°C.
™
Multi-Layer PCB, JEDEC Standard Test Boards
JA
A
Multi-Layer PCB, JEDEC Standard Test Boards
3.3V LVPECL FANOUT BUFFER
= Ambient Temperature
= Junction-to-Ambient Thermal Resistance
JA
HERMAL
VS
. A
IR
MAX
R
_MAX
F
ESISTANCE
LOW
= V
MAX
(3.465V, with all outputs switching) = 155.9mW + 120mW = 275.9mW
= 30mW/Loaded Output pair
CC_MAX
T
ABLE FOR
* I
EE_MAX
JA
FOR
= 3.465V * 45mA = 155.9mW
20 L
20-L
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
EAD
P
JA
JA
EAD
by Velocity (Meters per Second)
by Velocity (Meters per Second)
OWER
JA
VFQFN
* Pd_total + T
TSSOP, F
C
ORCED
ONSIDERATIONS
A
10
57.5°C/W
91.1°C/W
C
ONVECTION
0
0
TM
devices is 125°C.
50.3°C/W
86.7°C/W
1
1
ICS8535BGI-01 REV. B JANUARY 8, 2008
JA
must be used. Assuming a
45.1°C/W
84.6°C/W
2.5
2.5
PRELIMINARY