ics85354a Integrated Device Technology, ics85354a Datasheet
ics85354a
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ics85354a Summary of contents
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... INB nINB 0 QB nQB 1 SELA The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifica- tions without notice. 85354AK-01 PRELIMINARY D - IFFERENTIAL F ...
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OST US DAPTER OARDS FOR Host Adapter Board Protocol SerDes Controller PCI Bus 85354AK-01 PRELIMINARY D IFFERENTIAL OUTING ETWEEN NTERNAL AND INB nINB nQB 1 1 SELA 2 ICS85354-01 D ...
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WAPPABLE INKS TO EDUNDANT INB TX nINB SerDes Q B nQB RX Linecard 85354AK-01 PRELIMINARY D IFFERENTIAL WITCH ABRIC ARDS SELB LOOP SELA LOOP 1 ICS85354-01 ...
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ABLE IN ESCRIPTIONS ...
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BSOLUTE AXIMUM ATINGS Supply Voltage Negative Supply Voltage Inputs, V (LVPECL mode) I Inputs, V (ECL mode) I Outputs Continuous Current Surge Current Operating Temperature Range, TA -40°C to +85°C Storage ...
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T 4C. LVPECL DC C ABLE HARACTERISTICS ...
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2.375V ABLE HARACTERISTICS ...
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The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often ...
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P ARAMETER LVPECL V EE -0.375V to -1.465V UTPUT OAD EST IRCUIT nQx PART 1 Qx nQy PART 2 Qy tsk(pp ART TO ART KEW 80% Clock 20% ...
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IRING THE IFFERENTIAL NPUT TO Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias ...
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LVPECL IFFERENTIAL LOCK The IN/nIN accepts LVPECL, CML, SSTL and other differen- tial signals. Both V and V must meet the V SWING OH input requirements. Figures show interface ex- amples for the HiPerClockS IN/nIN ...
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T 3.3V LVPECL O ERMINATION FOR The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ...
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T 2.5V LVPECL O ERMINATION FOR Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to ter- minating 2V. For V = 2.5V, the 2.5V ...
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This section provides information on power dissipation and junction temperature for the ICS85354-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85354-01 is the sum of the core power plus the power ...
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Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure calculate worst case power dissipation into the load, use ...
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ABLE VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T C RANSISTOR OUNT The transistor count for ICS85354-01 is: 210 85354AK-01 PRELIMINARY D IFFERENTIAL R I ELIABILITY NFORMATION 16 L ...
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ACKAGE UTLINE UFFIX FOR T Reference Document: JEDEC Publication 95, MO-220 85354AK-01 PRELIMINARY D IFFERENTIAL VFQFN EAD ABLE ACKAGE IMENSIONS ...
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... While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications ...