ics87951 Integrated Device Technology, ics87951 Datasheet - Page 9

• Manufacturer Part Number: ics87951
• Description: Differential Or Lvcmos-input Lvcmos-output 2 9 180-mhz Clock Generator
• Manufacturer: Integrated Device Technology

F
R
I
CLK I
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
CLK/nCLK I
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS C
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
87951AYI
D
The CLK1 /nCLK1 accepts LVDS, LVPECL, LVHSTL, SSTL,
HCSL and other differential signals. Both V
meet the V
interface examples for the HiPerClockS CLK1/nCLK1 input driven
by the most common driver types. The input interfaces suggested
F
NPUTS
IGURE
IGURE
ECOMMENDATIONS FOR
IFFERENTIAL
NPUT
3.3V
:
3C. H
3A. H
1.8V
:
PP
LVPECL
ONTROL
and V
NPUT
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
3.3V LVPECL D
ICS H
I
I
P
P
Integrated
Circuit
Systems, Inc.
:
C
ER
ER
CMR
P
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
C
Zo = 50 Ohm
Zo = 50 Ohm
C
INS
I
P
input requirements. Figures 4A to 4D show
LOCK
LOCK
ER
:
C
I
S CLK/
NPUT
S CLK/
LOCK
U
NUSED
RIVER
S LVHSTL D
R1
50
3.3V
R3
125
I
R1
84
NTERFACE
N
N
CLK I
CLK I
R2
50
R4
125
I
R2
84
NPUT AND
CLK
nCLK
www.icst.com/products/hiperclocks.html
SWING
NPUT
NPUT
CLK
nCLK
3.3V
D
3.3V
RIVER
HiPerClockS
Input
IFFERENTIAL
and V
HiPerClockS
Input
D
D
O
RIVEN BY
RIVEN BY
UTPUT
OH
must
P
INS
9
-
TO
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
F
F
O
LVCMOS O
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
IGURE
IGURE
UTPUTS
-LVCMOS/LVTTL Z
3.3V
3.3V
LVDS_Driv er
3D. H
3B. H
LVPECL
:
UTPUT
3.3V LVPECL D
3.3V LVDS D
I
I
P
P
Zo = 50 Ohm
Zo = 50 Ohm
ER
ER
:
C
C
LOCK
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
S CLK/
S CLK/
RIVER
R1
50
RIVER
R3
50
L
ERO
N
N
R2
50
CLK I
CLK I
OW
R1
100
ICS87951I
CLK
nCLK
D
3.3V
S
REV. B NOVEMBER 23, 2005
NPUT
NPUT
ELAY
HiPerClockS
KEW
Input
CLK
nCLK
D
D
3.3V
, 1-
RIVEN BY
B
RIVEN BY
Receiv er
UFFER
TO
-9