ics87952-147 Integrated Device Technology, ics87952-147 Datasheet - Page 6

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ics87952-147

Manufacturer Part Number
ics87952-147
Description
High-fanout Lvcmos-input Lvcmos-output 1 11 180-mhz Clock Generator
Manufacturer
Integrated Device Technology
Datasheet
P
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS87952I-147 pro-
vides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. V
V
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10mF and a .01mF bypass
capacitor should be connected to each V
R
I
LVCMOS C
All control pins have internal pull-downs; additional resistance
is not required but can be added for additional protection. A
1kΩ resistor can be used.
87952AYI-147
NPUTS
DDO
OWER
ECOMMENDATIONS FOR
should be individually connected to the power supply
:
S
UPPLY
ONTROL
Integrated
Circuit
Systems, Inc.
P
F
INS
ILTERING
:
U
NUSED
T
ECHNIQUES
I
NPUT AND
A
LVCMOS / LVTTL C
DDA
www.icst.com/products/hiperclocks.html
PPLICATION
pin.
DD
O
, V
UTPUT
DDA
and
P
6
INS
I
NFORMATION
O
LVCMOS O
All unused LVCMOS output can be left floating. There should
be no trace attached.
UTPUTS
LOCK
:
F
UTPUT
IGURE
M
:
ULTIPLIER
1. P
V
V
DDA
DD
OWER
ICS87952I-147
.01μF
.01μF
/Z
S
L
UPPLY
OW
ERO
3.3V
10Ω
10 μF
S
F
D
ILTERING
KEW
ELAY
REV. B APRIL 10, 2006
, 1-
B
TO
UFFER
-11

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