ics86953-147 Integrated Device Technology, ics86953-147 Datasheet - Page 7

• Manufacturer Part Number: ics86953-147
• Description: Lvpecl-input Lvcmos-output 1 9 175-mhz Clock Zero-delay Buffer
• Manufacturer: Integrated Device Technology

86953BYI-147
PCLK/nPCLK C
The PCLK/ nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
and V
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
F
F
IGURE
IGURE
CMR
3C. H
3A. H
3.3V
3.3V
input requirements. Figures 3A to 3D show inter-
CML
LVPECL
BY A
BY A
I
I
P
P
Integrated
Circuit
Systems, Inc.
ER
ER
3.3V LVPECL D
CML D
C
C
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
LOCK
LOCK
S PCLK/
S PCLK/
RIVER
SWING
I
NPUT
3.3V
R1
50
and V
3.3V
R3
125
I
R1
84
NTERFACE
R2
50
N
N
RIVER
PCLK I
PCLK I
OH
R4
125
PCLK
nPCLK
R2
84
must meet the V
3.3V
D
www.icst.com/products/hiperclocks.html
HiPerClockS
PCLK/nPCLK
PCLK
nPCLK
IFFERENTIAL
NPUT
NPUT
3.3V
Input
HiPerClockS
D
D
RIVEN
RIVEN
PP
-
7
TO
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
F
F
IGURE
IGURE
-LVCMOS / LVTTL Z
3.3V
LVDS
3D. H
3B. H
2.5V
SSTL
BY A
BY AN
Zo = 50 Ohm
Zo = 50 Ohm
I
I
P
P
ER
ER
3.3V LVDS D
C
Zo = 60 Ohm
Zo = 60 Ohm
C
SSTL
LOCK
LOCK
R5
100
S PCLK/
S PCLK/
IN
ICS86953I-147
D
2.5V
R3
120
RIVER
R1
120
C1
C2
RIVER
ERO
L
R4
120
OW
N
R2
120
N
3.3V
R3
1K
PCLK I
PCLK I
R1
1K
D
S
PCLK
nPCLK
R4
1K
R2
1K
ELAY
3.3V
KEW
REV. B APRIL 23, 2004
PCLK
nPCLK
NPUT
NPUT
HiPerClockS
PCLK/nPCLK
3.3V
, 1-
B
HiPerClockS
PC L K /n PC LK
D
D
UFFER
RIVEN
RIVEN
TO
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