ics86953i-147 Integrated Device Technology, ics86953i-147 Datasheet - Page 7

• Manufacturer Part Number: ics86953i-147
• Description: Low Skew, 1-to-9 Ics86953i-147 Differential-to-lvcmos / Lvttl Zero Delay Buffer
• Manufacturer: Integrated Device Technology

ICS86953I-147
LVPECL C
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other dif-
ferential signals. Both differential inputs must meet the V
V
amples for the PCLK/nPCLK input driven by the most common
F
ICS86953BYI-147 REVISION B FEBRUARY 26, 2010
F
F
CMR
IGURE
IGURE
IGURE
input requirements. Figures 3A to 3E show interface ex-
3A. PCLK/nPCLK I
3C. PCLK/nPCLK I
3E. PCLK/nPCLK I
3.3V
3.3V
2.5V
LVPECL
CML
CML D
3.3V LVPECL D
SSTL
SSTL D
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
I
RIVER
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 60 Ohm
Zo = 60 Ohm
NPUT
RIVER
I
NTERFACE
NPUT
NPUT
NPUT
RIVER
3.3V
R1
50
2.5V
R3
120
3.3V
R3
125
R1
120
R1
84
D
D
D
R2
50
RIVEN
R4
120
RIVEN
RIVEN
R2
120
R4
125
R2
84
PCLK
nPCLK
3.3V
B
B
B
PCLK
nPCLK
PCLK
nPCLK
Y
Y
Y
3.3V
HiPerClockS
PCLK/nPCLK
A
A
3.3V
A
N
HiPerClockS
PCLK/nPCLK
Input
HiPerClockS
PP
and
7
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
F
F
driver types. The input interfaces suggested here are examples
only. If the driver is from another vendor, use their termination
recommendation. Please consult with the vendor of the driver
component to confirm the driver termination requirements.
IGURE
IGURE
3.3V
3.3V
3.3V LVPECL
3D. PCLK/nPCLK I
3B. PCLK/nPCLK I
CML Built-In Pullup
R5
100 - 200
B
3.3V LVPECL D
UILT
R6
100 - 200
-I
N
Zo = 50 Ohm
Zo = 50 Ohm
P
ULLUP
Zo = 50 Ohm
Zo = 50 Ohm
CML D
NPUT
NPUT
C1
C2
RIVER WITH
©2010 Integrated Device Technology, Inc.
3.3V
R3
84
D
D
R1
125
R1
100
RIVER
RIVEN
RIVEN
R4
84
R2
125
AC C
PCLK
nPCLK
B
B
3.3V
Y
Y
A
HiPerClockS
PCLK/nPCLK
A
PCLK
nPCLK
OUPLE
3.3V
HiPerClockS
PCLK/nPCLK