ics951403 Integrated Device Technology, ics951403 Datasheet
ics951403
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ics951403 Summary of contents
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... PCICLK_F 1 0 AGP (1: Power Groups VDD48, GND48 = 48MHz, PLL2 VDDREF, GNDREF= REF, X1, X2 VDD, GND = PLL Core ICS951403 Pin Configuration 48-Pin SSOP & TSSOP AGP SEL = FS0 CPU SDRAM PCICLK 0 0 100.00 100.00 33.33 66. 100.00 133.33 33.33 66 ...
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... ICS951403 General Description The ICS951403 is a main clock synthesizer chip for AMD-K7 based systems with ATI chipset. This provides all clocks required for such a system. The ICS951403 belongs to ICS new generation of programmable system clock generators. 2 programming I C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/ enabling individual clocks ...
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... ICS951403 ...
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... ICS951403 Byte 1: Output Control Register (1= enable disable ...
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... Byte 20: Slew Rate Control Register ICS951403 ...
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... ICS951403 VCO Programming Constrains VCO Frequency ...................... 150MHz to 500MHz VCO Divider Range ................ 8 to 519 REF Divider Range ................. 2 to 129 Phase Detector Stability .......... 0.3536 to 1.4142 Useful Formula VCO Frequency = 14.31818 x VCO/REF divider value Phase Detector Stabiliy = 14.038 x (VCO divider value) To program the VCO frequency for over-clocking. ...
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... V; Inputs with pull-up resistors Full load 3 Logic Inputs Logic Inputs X1 & X2 pins From target Freq. DD CPU Xover to SDRAM 1.5V CPU Xover to PCI 1.5V CPU Xover to AGP 1.5V 7 ICS951403 +0 MIN TYP MAX 0 0.3 0 -200 213 240 ...
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... ICS951403 Electrical Characteristics - REF 70°C; VDD=3.3V +/-5 PARAMETER SYMBOL Output High V OH5 Voltage V Output Low Voltage OL5 I Output High Current OH5 I Output Low Current OL5 t Rise Time r5 t Fall Time f5 1 Duty Cycle Jitter jcyc-cyc5 1 Guaranteed by design, not 100% tested in production. ...
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... CONDITIONS I = -18mA 18mA 2 0 0.4 V, VOH = 2 2.4 V, VOL = ICS951403 MIN TYP MAX UNITS 2.6 V 0 200 ps 104 250 ps MIN TYP MAX UNITS 2.4 V 0.4 V -22 mA ...
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... ICS951403 Electrical Characteristics - AGP [1: 70°C; VDD=3.3V +/-5 PARAMETER SYMBOL Output High Voltage 1 Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew t sk1 1 Jitter t jcyc-cyc 1 Guaranteed by design, not 100% tested in production. ...
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... General I C serial interface information for the ICS951403 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) sends a dummy command code • ICS clock will acknowledge • Controller (host) sends a dummy byte count • ...
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... ICS951403 2 Brief I C registers description for ICS951403 Programmable System Frequency Generator Register Name Functionality & Frequency Select Register Output Control Registers Vendor ID & Revision ID Registers Byte Count Read Back Register Watchdog Timer Count Register Watchdog Control Registers VCO Control Selection Bit ...
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... If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area more important to locate the series termination resistor close to the driver than the programming resistor. Fig ICS951403 ...
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... CPU_STOP asychronous input to the clock synthesizer used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS951403. All other clocks will continue to run while the CPUCLKs clocks are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...
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... PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS951403 used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS951403 internally. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock ...
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... Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS951403 device shown, the outputs Stop Low on the next falling edge after PD# goes low asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. ...
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... Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 17 ICS951403 In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN 2.41 2.80 .095 ...
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... AREA AREA Ordering Information ICS951403yGLF-T Example: ICS XXXX y G LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type Revision Designator (will not correlate with datasheet revision) Device Type Prefix 0486B—02/23/04 c 6.10 mm. Body, 0.50 mm. Pitch TSSOP ...