ics9db104 Integrated Device Technology, ics9db104 Datasheet - Page 2

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ics9db104

Manufacturer Part Number
ics9db104
Description
Four Output Differential Buffer For Pci-express
Manufacturer
Integrated Device Technology
Datasheet

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Pin Description
0767E—12/14/07
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN #
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE_1
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
SDATA
PD#
SRC_STOP#
HIGH_BW#
VDD
DIF_5#
DIF_5
OE_6
DIF_6#
DIF_6
VDD
GND
IREF
GNDA
VDDA
Integrated
Circuit
Systems, Inc.
PIN NAME
PIN TYPE
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
Power supply, nominal 3.3V
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Power supply, nominal 3.3V
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Asynchronous active low input pin used to power down the device. The
internal clocks are disabled and the VCO and the crystal are stopped.
Active low input to stop diff outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
Ground pin.
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
(Not recommended for new designs)
2
DESCRIPTION
ICS9DB104

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