ics9fg1901 Integrated Device Technology, ics9fg1901 Datasheet - Page 2

• Manufacturer Part Number: ics9fg1901
• Description: Frequency Generator For P4? ? ? ? ? Cpu, Pci Express? ? ? ? ? & Fully Buffered Dimm Clocks
• Manufacturer: Integrated Device Technology

Pin Description
0962E—01/02/07
PIN #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
IREF
GNDA
VDDA/PD#
HIGH_BW#
FS_A_410
DIF_0
DIF_0#
DIF_1
DIF_1#
GND
VDD
DIF_2
DIF_2#
DIF_3
DIF_3#
DIF_4
DIF_4#
OE_01234#
SMBCLK
SMBDAT
OE5#
DIF_5
DIF_5#
OE6#
DIF_6
DIF_6#
VDD
GND
OE7#
DIF_7
DIF_7#
OE8#
DIF_8
DIF_8#
SMB_A0
SMB_A1
Integrated
Circuit
Systems, Inc.
PIN NAME
PIN TYPE
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Ground pin.
Ground pin.
This pin establishes the reference current for the differential current-mode output
pairs. This pin requires a fixed precision resistor tied to ground in order to
establish the appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core that also functions as Power Down. Collapsing this
power supply places the device in Power Down mode.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
CK410 FSA. Refer to input electrical characteristics for Vil_FS and Vih_FS
threshold values.
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.
1 = tri-state outputs, 0 = enable outputs
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
SMBus address bit 0 (LSB)
SMBus address bit 1
3.3V tolerant low threshold input for CPU frequency selection. This pin requires
2
DESCRIPTION
ICS9FG1901