ics9lprs365 Integrated Device Technology, ics9lprs365 Datasheet - Page 3

• Manufacturer Part Number: ics9lprs365
• Description: 64-pin Ck505 W/fully Integrated Voltage Regulator + Integrated Series Resistor
• Manufacturer: Integrated Device Technology

TSSOP Pin Description (Continued)
1218—09/01/10
PIN #
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
27MHz_NonSS/SRCT1/SE1
27MHz_SS/SRCC1/SE2
GND
VDDPLL3_IO
SRCT2/SATAT
SRCC2/SATAC
GNDSRC
SRCT3/CR#_C
SRCC3/CR#_D
VDDSRC_IO
SRCT4
SRCC4
GNDSRC
SRCT9
SRCC9
SRCC11/CR#_G
PIN NAME
TYPE
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
PWR
OUT
OUT
I/O
I/O
I/O
I/O
I/O
True clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select determines the power-up
default, 1=27MHz non-spread SE clock, 0 = LCD_SST 100MHz differential clock. See table 2 for more
information.
Complement clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select determines the
power-up default, 1=27MHz spread SE clock, 0 = LCD_SSC 100MHz differential clock. See table 2 for
more information.
Ground pin for SRC / SE1 and SE2 clocks, PLL3.
True clock of differential SRC/SATA clock pair.
Complement clock of differential SRC/SATA clock pair.
Ground pin for SRC clocks.
True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of
SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output
must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin
can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or SRC4
pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of
SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output
must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin
can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
0 = CR#_D controls SRC1 pair (default),
1= CR#_D controls SRC4 pair
True clock of differential SRC clock pair 4
Complement clock of differential SRC clock pair 4
Ground pin for SRC clocks.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
SRC11 complement /Clock Request control for SRC9 pair
The power-up default is SRC11#, but this pin may also be used as a Clock Request control of SRC9 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in
byte 3, bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
1.05V to 3.3V from external power supply
Byte 5, bit 2
Byte 5, bit 0
1.05V to 3.3V from external power supply
3
DESCRIPTION
ICS9LPRS365
Datasheet