ics9ex21501 Integrated Device Technology, ics9ex21501 Datasheet - Page 5

• Manufacturer Part Number: ics9ex21501
• Description: 15 Output Pcie G2/qpi Differential Buffer With 2 1 Input Mux
• Manufacturer: Integrated Device Technology

IDT
1
2
TA = T
Input High Voltage - DIF_IN
Input Jitter - Cycle to Cycle
1
2
TA = T
1
2
3
4
5
6
Electrical Characteristics - Absolute Maximum Ratings
Electrical Characteristics - Clock Input Parameters
Input Low Voltage - DIF_IN
Electrical Characteristics - Phase Jitter Parameters
3.3V Logic Supply Voltage
3.3V Core Supply Voltage
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through +/-75mV window centered around differential zero
Input Slew Rate - DIF_IN
Operation under these conditions is neither implied nor guaranteed.
Input Amplitude - DIF_IN
Guaranteed by design and characterization, not 100% tested in production.
Applies to all outputs. Device driven by IDT CK410B+ (932S421CGLF) or equivalent
See http://www.pcisig.com for complete specs
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
First number is Low BW, second number is Hi BW.
Calculated from Intel-supplied Clock Jitter Tool v 1.6.4, with 7.8M rolloff
For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2
Phase Jitter, PLL Mode
9EX21501
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
Input Leakage Current
Junction Temperature
®
Storage Temperature
Input ESD protection
Input Common Mode
Additive Phase Jitter,
15 Output PCIe G2/QPI Differential Buffer with 2:1 Input Mux
Input High Voltage
Input High Voltage
Input Low Voltage
Voltage - DIF_IN
Input Duty Cycle
PARAMETER
PARAMETER
PARAMETER
Bypass mode
COM
COM
or T
or T
IND;
IND;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
SYMBOL
SYMBOL
SYMBOL
ESD prot
t
t
t
t
V
jphPCIeG1
jphPCIeG2
jphPCIeG1
jphPCIeG2
VDDA
V
V
V
t
t
V
dv/dt
J
VDD
jphQPI
jphQPI
SWING
V
IHSMB
d
V
DIFIn
Ts
IHDIF
ILDIF
I
COM
Tj
IN
tin
IH
IL
Measurement from differential wavefrom
(133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
(133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
1.5MHz < f < Nyquist (50MHz)
1.5MHz < f < Nyquist (50MHz)
Common Mode Input Voltage
(single-ended measurement)
(single-ended measurement)
Except for SMBus interface
SMBus clock and data pins
Differential Measurement
PCIe Gen 2 High Band
PCIe Gen 2 High Band
Measured differentially
V
PCIe Gen 2 Lo Band
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
10kHz < f < 1.5MHz
Peak to Peak value
Human Body Model
IN
Differential inputs
Differential inputs
CONDITIONS
CONDITIONS
= V
CONDITIONS
PCIe Gen 1
PCIe Gen 1
DD ,
QPI
QPI
V
IN
= GND
5
V
GND-0.5
SS
2000
MIN
MIN
MIN
600
300
300
-65
0.4
45
-5
0
- 300
0.25/0.28
1.2/1.5
2.1/2.7
32/42
TYP
TYP
TYP
0.30
0.25
800
400
750
0.0
50
50
0
2
2
V
DD
MAX
MAX
1150
1000
1450
MAX
5.5V
150
125
300
125
0.3
0.5
4.6
4.6
3.1
0.5
0.4
55
86
10
+0.5V
8
5
3
UNITS NOTES
UNITS NOTES
UNITS
(rms)
(rms)
(rms)
(rms)
(rms)
(rms)
V/ns
(p-p)
(p-p)
mV
mV
mV
mV
uA
ps
ps
ps
ps
ps
ps
ps
ps
ps
°
°C
%
V
V
V
V
V
V
C
Datasheet
1,2,3,4
Notes
1,2,4
1,2,4
1,4,5
1,2,3
1,2,6
1,2,6
1,5,6
1,2
1,2
1,2
1578—01/18/11
1
1
1
1
1
1
1
1
1
1
1
1
1