ics9p935 Integrated Device Technology, ics9p935 Datasheet
ics9p935
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ics9p935 Summary of contents
Page 1
... CLK_INT 9 CLK_INC 10 VDD2.5/1.8 11 DDRT2 12 DDRC2 13 GND 14 Control Logic PLL 1 DATASHEET ICS9P935 28 GND 27 DDRC5 26 DDRT5 25 VDD2.5/1.8 24 GND 23 DDRC4 22 DDRT4 21 VDD2.5/1.8 20 SDATA 19 SCLK 18 FB_IN 17 FB_OUT 16 DDRT3 15 DDRC3 28-SSOP/TSSOP FB_OUT DDRT0 DDRC0 DDRT1 DDRC1 DDRT2 DDRC2 DDRT3 DDRC3 DDRT4 DDRC4 DDRT5 DDRC5 ICS9P935 REV H 12/1/08 ...
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... Data pin for SMBus circuitry, 3.3V tolerant. PWR Power supply, nominal 2.5V or 1.8V OUT "True" Clock of differential pair output. OUT "Complementary" Clock of differential pair output. PWR Ground pin. PWR Power supply, nominal 2.5V or 1.8V OUT "True" Clock of differential pair output. OUT "Complementary" Clock of differential pair output. PWR Ground pin. 2 ICS9P935 REV H 12/1/08 ...
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... 1.8V Iin = -18mA DDQ I = -100µ -9mA OH I =100µ =9mA GND GND or V OUT DD 3 +0.5 V MIN TYP MAX ±250 ±10 100 300 500 -1.2 -0.2 DD 1.1 0.1 0 ICS9P935 UNITS µA µA µA mA µ REV H 12/1/08 ...
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... =1.9V OUT and is the voltage DD 4 MIN TYP 1.7 1.8 0. -0.3 1.5 GND - 0.3 0 GND 0 ICS9P935 MAX UNITS 1 ± °C ...
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... MIN MAX UNITS 125 500 MHz 160 400 MHz µs MIN TYP MAX -40 -75 1 2.5 0.5 1.5 2 -50 -50 0 30.00 0.00 -0. ICS9P935 UNITS v/ns v/ kHz % REV H 12/1/08 ...
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... 2.3V, DDQ min to max 2.3V DDQ I = GND GND or V OUT DD 6 MIN TYP MAX 5 5 250 100 -18 - ±10 -1 0.1 DDQ 1.7 0.1 0 ICS9P935 UNITS µA µA mA µ REV H 12/1/08 ...
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... DDR I/DDR II Phase Lock Loop Zero Delay Buffer TM TM IDT /ICS CONDITIONS VDD DDRT,DDRC IL DDRT,DDRC DC - DDRT AC - DDRT MIN TYP 2.3 2.5 0 0.18 2.1 DD -0.3 V 0. and is the voltage ICS9P935 MAX UNITS 0.2 V - °C REV H 12/1/08 ...
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... T -T 100MHz to 200MHz cyc cyc 4 T skew /t , were the cycle ( MIN MAX UNITS 45 600 MHz 95 233 MHz µs MIN TYP MAX UNITS 3.5 ns 3 -100 100 V/ V/ ICS9P935 REV H 12/1/08 ...
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... ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer 2 General I C serial interface information for the ICS9P935 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D4 • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ...
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... See Table 2: 7-Step Skew Programming Table PWD - - PWD Writing to this register will configure how many bytes 0 will be read back, default bytes LSB -500 ps -400 ps -300 ps N/A N/A -200 ps N/A N/A -100 ps N/A N/A 0.0 ps ICS9P935 REV H 12/1/08 ...
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... MIN -- 2.00 -- 0.05 -- .002 1.65 1.85 .065 0.22 0.38 .009 0.09 0.25 .0035 SEE VARIATIONS SEE VARIATIONS 7.40 8.20 .291 5.00 5.60 .197 0.65 BASIC 0.0256 BASIC 0.55 0.95 .022 SEE VARIATIONS SEE VARIATIONS 0° 8° 0° D mm. D (inch) MIN MAX MIN 9.90 10.50 .390 ICS9P935 MAX .079 -- .073 .015 .010 .323 .220 .037 8° MAX .413 REV H 12/1/08 ...
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... BASIC E1 4.30 4.50 e 0.65 BASIC L 0.45 0.75 N SEE VARIATIONS α 0° 8° aaa -- 0.10 D mm. N MIN MAX 28 9.60 9.80 ICS9P935 In Inches COMMON DIMENSIONS MIN MAX -- .047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° ...
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... ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer Revision History Rev. Issue Date Description A 2/8/2007 Final Release. B 6/4/2007 Fixed various typos. C 6/14/2007 Added TSSOP Ordering Information. 1. Updated Output Features: Max Frequency Supported. D 6/20/2007 2. Updated DDRI/DDRII Max Clock Frequency. 1. Updated Supply Voltage. ...