ics581 Integrated Device Technology, ics581 Datasheet - Page 6

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ics581

Manufacturer Part Number
ics581
Description
Zero Delay Glitch-free Clock Multiplexer
Manufacturer
Integrated Device Technology
Datasheet

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AC Electrical Characteristics
IDT™ / ICS™ ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
ICS581-01/02
ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Note 1: Assumes clocks with same rise times, measured at VDD/2.
Note 2: Assumes identically loaded outputs with identical rise times, measured at VDD/2. The maximum skew between any two
clocks is 250 ps not 500 ps.
Note 3: Time taken for output to lock to new clock when mux selection changed from INA to INB.
Note 4. With 50 MHz on INA and 150 MHz on INB.
Note 5: With 100 MHz on both INA and INB, 180° out of phase.
Input Capacitance
Output High Voltage
Output Low Voltage
Short Circuit Current
On-chip Pull-up
Resistor
Input Frequency
Input Clock Duty Cycle
Skew
Transition Detector
Timeout
ICS581-02 only
Frequency Transition Time
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Absolute Output Clock
Period Jitter
One Sigma Output Clock
Period Jitter
Parameter
Parameter
Symbol
V
R
V
C
I
OS
OH
Symbol
OL
PU
IN
t
t
SKEW
TRAN
t
t
t
t
f
OR
OF
JA
JA
IN
I
I
OH
OL
Conditions
= 12 mA
at VDD/2
selected input clock to
FBIN, Note 1
between any output
clocks, Note 2
DIV = 0
DIV = 1
50 to 150 MHz, Note 3, 4
100 to 100 MHz, Note 3,
5
0.8 V to 2.0 V
2.0 V to 0.8 V
less than 133 MHz
at VDD/2, no load
greater than 133 MHz
at VDD/2, no load
with S0=S1=1
at VDD/2, no load
Deviation from mean
= -12 mA
Conditions
6
S1=0, OE1=0,
SELA, DIV pins
VDD-0.5
Min.
Min.
-250
-250
30
32
45
40
40
6
2
Typ.
Typ.
±150
±70
250
48
70
40
5
0
0
3
4
1
1
Max.
200
250
250
200
70
64
10
55
60
60
4
2
2
Max.
ZDB AND MULTIPLEXER
0.5
ICS581-01/02
periods
periods
Units
MHz
INB
INB
ps
ps
µs
µs
ns
ns
ps
ps
%
%
%
%
Units
mA
kΩ
pF
V
V
REV H 050206

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