ics621 Integrated Device Technology, ics621 Datasheet - Page 2

• Manufacturer Part Number: ics621
• Description: Low Skew 1 To 4 Clock Buffer
• Manufacturer: Integrated Device Technology

Pin Assignment (8-pin SOIC)
Pin Descriptions
External Components
IDT™ / ICS™ LOW SKEW 1 TO 4 CLOCK BUFFER
Number
ICS621
LOW SKEW 1 TO 4 CLOCK BUFFER
Pin
1
2
3
4
5
6
7
8
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 µ F
should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible. A 33 Ω series
terminating resistor may be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the ICS621 is capable of, careful attention must be paid to board layout.
Essentially, all four outputs must have identical terminations, identical loads and identical trace geometries. If they
do not, the output skew will be degraded. For example, using a 30 Ω series termination on one output (with 33 Ω on
the others) will cause at least 15 ps of skew.
ICLK
Q1
Q2
Q3
Name
ICLK
GND
VDD
Pin
OE
Q1
Q2
Q3
Q4
4
1
2
3
Output
Output
Output
Output
Power
Power
Type
Input
Input
Pin
Clock Input. 3.3 V tolerant input.
Clock Output 1.
Clock Output 2.
Clock Output 3.
Clock Output 4.
Connect to ground.
Output Enable. Tri-states outputs when low. Connect to VDD for normal operation.
Connect to +1.2 V or +1.8 V.
8
6
5
7
Q4
OE
VDD
GND
2
Pin Assignment (8-pin DFN)
Pin Description
ICLK
Q2
Q3
Q1
4
1
8
5
ICS621
FAN OUT BUFFER
Q4
OE
VDD
GND
REV B 030907