ics411 Integrated Device Technology, ics411 Datasheet - Page 3

• Manufacturer Part Number: ics411
• Description: Pc Peripheral Clock
• Manufacturer: Integrated Device Technology

IDT™ / ICS™ PC PERIPHERAL CLOCK
ICS411
PC PERIPHERAL CLOCK
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50 Ω trace (a
commonly used trace impedance), place a 33 Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20 Ω .
Decoupling Capacitor
As with any high performance mixed-signal IC, the
ICS411 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD pin and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output
Absolute Maximum Ratings
Recommended Operation Conditions
Stresses above the ratings listed below can cause permanent damage to the ICS411. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Item
3
phase noise, the following guidelines should be
observed.
1) 0.01µF decoupling capacitors should be mounted on
the component side of the board as close to the VDD
pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via.
2) To minimize EMI the 33 Ω series termination resistor,
if needed, should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS411. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
+3.00
Min.
0
7 V
-0.5 V to VDD+0.5 V
0 to +70 ° C
-65 to +150 ° C
125 ° C
260 ° C
Typ.
–
Rating
+3.60
Max.
+70
ICS411
CLOCK SYNTHESIZER
Units
REV C 062005
° C
V