is61lv12824 Integrated Silicon Solution, Inc., is61lv12824 Datasheet - Page 10

• Manufacturer Part Number: is61lv12824
• Description: 128k X 24 High-speed Cmos Static Ram With 3.3v Supply
• Manufacturer: Integrated Silicon Solution, Inc.

IS61LV12824
10
WRITE CYCLE NO. 3
ADDRESS
Note:
1. The internal Write time is defined by the overlap of CE1 and CE2 = LOW, CE2 = HIGH and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is
referenced to the rising or falling edge of the signal that terminates the Write.
D
CE1
CE2
OUT
WE
D
OE
IN
LOW
LOW
HIGH
t
DATA UNDEFINED
SA
(1)
(WE Controlled: OE
t
t
I S
AW
HZWE
LOW
VALID ADDRESS
DURING
t
t
PWE2
WC
Integrated Silicon Solution, Inc. — 1-800-379-4774
W
HIGH-Z
RITE
t
C
SD
YLE
DATA
)
IN
VALID
t
HD
t
LZWE
t
HA
ISSI
CE2_WR3.eps
06/22/05
Rev. D
®