is61lp6432a Integrated Silicon Solution, Inc., is61lp6432a Datasheet

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is61lp6432a

Manufacturer Part Number
is61lp6432a
Description
64k X 32, 64k X 36 Synchronous Pipelined Static Ram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet

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IS61LP6432A
IS61LP6436A
64K x 32, 64K x 36 SYNCHRONOUS
PIPELINED STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
• Pentium™ or linear burst sequence control using
• Three chip enables for simple depth expansion
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP package
• Power-down snooze mode
• Power Supply:
• Lead-free available
FAST ACCESS TIME
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
09/02/05
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
control
MODE input
and address pipelining
+3.3V V
+3.3V or 2.5V V
Symbol
t
t
KC
KQ
DD
Parameter
Clock Access Time
Cycle Time
Frequency
DDQ
(I/O)
-166
166
3.5
6
-133
133
7.5
DESCRIPTION
The
static RAM designed to provide a burstable, high-perfor-
mance memory for high speed networking and communica-
tion applications. The IS61LP6432A is organized as 64K
words by 32 bits and the IS61LP6436A is organized as 64K
words by 36 bits. Fabricated with
technology, the device integrates a 2-bit burst counter, high-
speed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass
through registers controlled by a positive-edge-triggered
single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQa, BW2 controls DQb, BW3 controls
DQc, BW4 controls DQd, conditioned by BWE being
LOW. A LOW on GW input would cause all bytes to be
written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
4
ISSI
IS61LP6432A/36A is a high-speed synchronous
Units
MHz
ns
ns
SEPTEMBER 2005
ISSI
ISSI
's advanced CMOS
®
1

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is61lp6432a Summary of contents

Page 1

... IS61LP6432A/36A is a high-speed synchronous static RAM designed to provide a burstable, high-perfor- mance memory for high speed networking and communica- tion applications. The IS61LP6432A is organized as 64K words by 32 bits and the IS61LP6436A is organized as 64K words by 36 bits. Fabricated with technology, the device integrates a 2-bit burst counter, high- speed SRAM core, and high-drive capability outputs into a single monolithic circuit ...

Page 2

... IS61LP6432A IS61LP6436A BLOCK DIAGRAM CLK ADV ADSC ADSP 16 A15-A0 GW BWE BW4 BW3 BW2 BW1 CE CE2 CE2 OE 2 MODE A0' Q0 CLK A0 BINARY COUNTER A1 CLR MEMORY ARRAY ADDRESS REGISTER CE CLK x32/x36 D Q DQd BYTE WRITE REGISTERS CLK D Q DQc ...

Page 3

... IS61LP6432A IS61LP6436A PIN CONFIGURATION 100-Pin TQFP 100 DQPc 1 2 DQc1 3 DQc2 4 VDDQ 5 VSS 6 DQc3 7 DQc4 DQc5 8 9 DQc6 VSS 10 11 VDDQ 12 DQc7 13 DQc8 VDD 16 NC VSS 17 18 DQd1 DQd2 19 20 VDDQ ...

Page 4

... IS61LP6432A IS61LP6436A PIN CONFIGURATION 100-Pin TQFP 100 DQc1 3 DQc2 4 VDDQ VSS 5 6 DQc3 DQc4 7 8 DQc5 DQc6 9 10 VSS 11 VDDQ 12 DQc7 13 DQc8 VDD VSS DQd1 18 19 DQd2 20 VDDQ ...

Page 5

... IS61LP6432A IS61LP6436A TRUTH TABLE Address Operation Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst ...

Page 6

... IS61LP6432A IS61LP6436A INTERLEAVED BURST ADDRESS TABLE (MODE = V External Address 1st Burst Address LINEAR BURST ADDRESS TABLE (MODE = Vss) A1', A0' = 1,1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter T Storage Temperature STG P Power Dissipation D I Output Current (per I/O) OUT Voltage Relative to Vss for I/O Pins ...

Page 7

... IS61LP6432A IS61LP6436A OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current LI I Output Leakage Current ...

Page 8

... IS61LP6432A IS61LP6436A (1,2) CAPACITANCE Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times ...

Page 9

... IS61LP6432A IS61LP6436A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load 2.5V I/O OUTPUT LOAD EQUIVALENT OUTPUT Figure 3 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 09/02/05 Unit 1.25V See Figures 3 and 4 +2 ...

Page 10

... IS61LP6432A IS61LP6436A READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter f (3) Clock Frequency MAX (3) t Cycle Time KC t Clock High Time KH t (3) Clock Low Time KL t (3) Clock Access Time KQ (1) t Clock High to Output Invalid KQX (1,2) t Clock High to Output Low-Z KQLZ ...

Page 11

... IS61LP6432A IS61LP6436A READ/WRITE CYCLE TIMING CLK ADSP ADSC ADV A15-A0 RD1 BWE BW4-BW1 t t CES CEH CES CEH CE2 t t CES CEH CE2 t OEQ OE t OELZ High-Z DATA OUT t KQLZ High-Z DATA IN Single Read Integrated Silicon Solution, Inc. — ...

Page 12

... IS61LP6432A IS61LP6436A WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter t (1) Cycle Time KC t (1) Clock High Time KH (1) t Clock Low Time KL (1) t Address Setup Time AS (1) t Address Status Setup Time SS t (1) Write Setup Time WS t (1) Data In Setup Time DS (1) t Chip Enable Setup Time ...

Page 13

... IS61LP6432A IS61LP6436A WRITE CYCLE TIMING CLK ADSP ADSC ADV must be inactive for ADSP Write ADV A15-A0 WR1 BWE t WS BW4-BW1 WR1 t t CES CEH CES CEH CE2 t t CES CEH CE2 OE High-Z DATA ...

Page 14

... IS61LP6432A IS61LP6436A SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol Parameter t (3) Cycle Time KC t (3) Clock High Time KH (3) t Clock Low Time KL (3) t Clock Access Time KQ (1) t Clock High to Output Invalid KQX t (1,2) Clock High to Output Low-Z KQLZ t (1,2) Clock High to Output High-Z ...

Page 15

... IS61LP6432A IS61LP6436A SNOOZE AND RECOVERY CYCLE TIMING CLK ADSP ADSC ADV A15-A0 RD1 GW BWE BW4-BW1 t t CES CEH CES CEH CE2 t t CES CEH CE2 t OEQ OE t OELZ High-Z DATA OUT t KQLZ High-Z DATA IN ZZ Single Read Integrated Silicon Solution, Inc. — ...

Page 16

... IS61LP6432A IS61LP6436A ORDERING INFORMATION: IS61LP6432A Commercial Range: 0°C to +70°C Speed Order Part Number 133 MHz IS61LP6432A-133TQ Industrial Range: –40°C to +85°C Speed Order Part Number 133 MHz IS61LP6432A-133TQI 133 MHz IS61LP6432A-133TQLI ORDERING INFORMATION: IS61LP6436A Commercial Range: 0°C to +70°C ...

Page 17

... E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF Integrated Silicon Solution, Inc. — 1-800-379-4774 PK13197LQ Rev. D 05/08/ Millimeters Inches Max Min Max Min 128 0.063 — 1.60 — 0.05 0.15 0.002 0.006 1.35 1.45 0.053 0.057 ...

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