is61lf25636a Integrated Silicon Solution, Inc., is61lf25636a Datasheet

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... IS61LF25636A IS61VF25636A IS61LF51218A IS61VF51218A 256K x 36, 512K SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • ...

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... IS61LF25636A IS61LF51218A BLOCK DIAGRAM CLK ADV ADSC ADSP 18/ BWE BW(a-d) x18: a,b x36: a-d CE CE2 CE2 POWER ZZ DOWN OE 2 IS61VF25636A MODE A0' Q0 CLK A0 BINARY COUNTER A1 CLR MEMORY ARRAY 16/17 18/ ADDRESS REGISTER CE CLK 36 DQ(a-d) BYTE WRITE REGISTERS CLK 2/4/8 INPUT D Q REGISTERS ...

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... IS61LF25636A IS61LF51218A 165-PIN BGA 165-Ball, 13x15 mm BGA BOTTOM VIEW Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. C 10/18/07 IS61VF25636A IS61VF51218A 119-PIN BGA 119-Ball, 14x22 mm BGA BOTTOM VIEW 3 ...

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... IS61LF25636A IS61LF51218A 119 BGA PACKAGE PIN CONFIGURATION DDQ B NC CE2 DQc DQPc Vss E DQc DQc Vss F V DQc Vss DDQ BWc G DQc DQc H DQc DQc Vss DDQ DD K DQd DQd Vss BWd L DQd DQd M V DQd ...

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... IS61LF25636A IS61LF51218A 119 BGA PACKAGE PIN CONFIGURATION 512K 18 (TOP VIEW DDQ B NC CE2 DQb NC Vss E NC DQb Vss Vss DDQ BWb G NC DQb H DQb NC Vss DDQ DQb Vss L DQb NC Vss M V DQb ...

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... IS61LF25636A IS61LF51218A 165 PBGA PACKAGE PIN CONFIGURATION 256K 36 (TOP VIEW CE2 C DQPc NC V DDQ D DQc DQc V DDQ E DQc DQc V DDQ F DQc DQc V DDQ G DQc DQc V DDQ H NC Vss NC J DQd DQd V DDQ K DQd DQd V DDQ L DQd ...

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... IS61LF25636A IS61LF51218A 165 PBGA PACKAGE PIN CONFIGURATION 512K 18 (TOP VIEW CE2 DDQ D NC DQb V DDQ E NC DQb V DDQ F NC DQb V DDQ G NC DQb V DDQ H NC Vss NC J DQb NC V DDQ K DQb NC V DDQ L DQb ...

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... IS61LF25636A IS61LF51218A PIN CONFIGURATION 100 DQPc 1 2 DQc 3 DQc 4 VDDQ 5 VSS DQc 6 DQc 7 DQc 8 DQc 9 VSS 10 VDDQ 11 12 DQc 13 DQc VDD VSS 18 DQd 19 DQd 20 VDDQ VSS 21 DQd 22 DQd 23 DQd 24 DQd ...

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... IS61LF25636A IS61LF51218A PIN CONFIGURATION 100 VDDQ 5 VSS DQb 8 DQb 9 10 VSS VDDQ 11 12 DQb 13 DQb VDD 16 NC VSS 17 18 DQb 19 DQb VDDQ 20 21 VSS DQb ...

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... IS61LF25636A IS61LF51218A TRUTH TABLE (1-8) ADDRESS CE OPERATION Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Snooze Mode, Power-Down None Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst ...

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... IS61LF25636A IS61LF51218A INTERLEAVED BURST ADDRESS TABLE (MODE = V External Address 1st Burst Address LINEAR BURST ADDRESS TABLE (MODE = VSS) A1', A0' = 1,1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter T Storage Temperature STG P Power Dissipation D I Output Current (per I/O) OUT Voltage Relative to Vss for I/O Pins ...

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... IS61LF25636A IS61LF51218A OPERATING RANGE (IS61LFxxxxx) Range Ambient Temperature Commercial 0°C to +70°C Industrial -40°C to +85°C OPERATING RANGE (IS61VFxxxxx) Range Ambient Temperature Commercial 0°C to +70°C Industrial -40°C to +85°C DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions V Output HIGH Voltage Output LOW Voltage ...

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... IS61LF25636A IS61LF51218A (1,2) CAPACITANCE Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times ...

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... IS61LF25636A IS61LF51218A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT Z = 50Ω O OUTPUT Figure 3 14 IS61VF25636A Unit 0V to 2.5V 1.5 ns 1.25V OUTPUT 50Ω 1.25V Integrated Silicon Solution, Inc. — 1-800-379-4774 IS61VF51218A 1,667 Ω ...

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... IS61LF25636A IS61LF51218A READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter fmax Clock Frequency t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ t (2) Clock High to Output Invalid KQX t (2,3) Clock High to Output Low-Z KQLZ (2,3) t Clock High to Output High-Z KQHZ ...

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... IS61LF25636A IS61LF51218A READ/WRITE CYCLE TIMING CLK ADSP t SS ADSC ADV Address RD1 BWE BWd-BWa t t CES CEH CES CEH CE2 t t CES CEH CE2 t OELZ t OEQ OE High-Z DATA OUT t KQLZ t KQ High-Z DATA ...

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... IS61LF25636A IS61LF51218A WRITE CYCLE TIMING CLK ADSP ADSC ADV must be inactive for ADSP Write ADV Address WR1 BWE t WS BWd-BWa WR1 t t CES CEH CES CEH CE2 t t CES CEH CE2 OE High-Z DATA ...

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... IS61LF25636A IS61LF51218A SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol Parameter I Current during SNOOZE MODE active to input ignored PDS t ZZ inactive to input sampled PUS t ZZ active to SNOOZE current ZZI t ZZ inactive to exit SNOOZE current RZZI SNOOZE MODE TIMING CLK t PDS ZZ setup cycle ...

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... IS61LF25636A IS61LF51218A IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) The IS61LF/VF25636A and IS61LF/VF51218A have a serial boundary scan Test Access Port (TAP) in the PBGA package only. This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM ...

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... IS61LF25636A IS61LF51218A TEST DATA OUT (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register ...

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... IS61LF25636A IS61LF51218A TAP INSTRUCTION SET Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149 ...

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... IS61LF25636A IS61LF51218A INSTRUCTION CODES Code Instruction Description 000 EXTEST Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. 001 IDCODE Loads the ID register with the vendor ID code and places the register between TDI and TDO ...

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... IS61LF25636A IS61LF51218A TAP Electrical Characteristics Over the Operating Range Symbol Parameter V Output HIGH Voltage OH1 V Output HIGH Voltage OH2 V Output LOW Voltage OL1 V Output LOW Voltage OL2 V Input HIGH Voltage IH V Input LOW Voltage IL I Input Load Current X Notes: 1. All Voltage referenced to Ground. ...

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... IS61LF25636A IS61LF51218A TAP AC TEST CONDITIONS Input pulse levels 0 to 2.5V/0 to 3.0V Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage TAP TIMING 1 t THTH TCK TMS TDI TDO 24 IS61VF25636A TAP Output Load Equivalent 1ns 1.25V/1.5V 1 ...

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... IS61LF25636A IS61LF51218A 119 BGA BOUNDARY SCAN ORDER (256K X 36) Signal Bump Bit # Name ID Bit # DQa DQa DQa DQa DQa DQa DQa ...

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... IS61LF25636A IS61LF51218A 165 PBGA BOUNDARY SCAN ORDER (x 36) Signal Bump Bit # Name ID Bit # 1 MODE 11P 10P 10R 11R 11H 31 12 DQa 11N 32 13 DQa 11M ...

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... IS61LF25636A IS61LF51218A 165 PBGA BOUNDARY SCAN ORDER (x 18) Signal Bump Bit # Name ID Bit # 1 MODE 11P 10P 10R 11R 11H 11N 11M 11L ...

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... IS61LF25636A-7.5B3 IS61LF51218A-6.5TQ IS61LF51218A-6.5B2 IS61LF51218A-6.5B3 IS61LF51218A-7.5TQ IS61LF51218A-7.5B2 IS61LF51218A-7.5B3 Order Part Number IS61LF25636A-6.5TQI IS61LF25636A-6.5B2I IS61LF25636A-6.5B3I IS61LF25636A-7.5TQI IS61LF25636A-7.5TQLI IS61LF25636A-7.5B2I IS61LF25636A-7.5B3I IS61LF51218A-6.5TQI IS61LF51218A-6.5B2I IS61LF51218A-6.5B3I IS61LF51218A-7.5TQI IS61LF51218A-7.5TQLI IS61LF51218A-7 ...

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... IS61LF25636A IS61LF51218A ORDERING INFORMATION (V Commercial Range: 0°C to +70°C Configuration Access Time 256Kx36 6.5 256Kx36 7.5 512Kx18 6.5 512Kx18 7.5 Industrial Range: -40°C to +85°C Configuration Access Time 256Kx36 6.5 256Kx36 7.5 512Kx18 6.5 512Kx18 7.5 Note: 1. For 100 TQFP, 2CE option contact SRAM Marketing at sram@issi.com Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev ...

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... BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — ...

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... Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — ...

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... E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF Integrated Silicon Solution, Inc. — 1-800-379-4774 PK13197LQ Rev. D 05/08/ Millimeters Inches Max Min Max Min 128 0.063 — 1.60 — 0.05 0.15 0.002 0.006 1.35 1.45 0.053 0.057 ...