mpc9351 Integrated Device Technology, mpc9351 Datasheet - Page 3

• Manufacturer Part Number: mpc9351
• Description: Low Voltage Pll Clock Driver
• Manufacturer: Integrated Device Technology

IDT™ Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9351
Low Voltage PLL Clock Driver
Advanced Clock Drivers Devices
Freescale Semiconductor
Table 1. Pin Descriptions
Table 2. Function Table
Table 3. Absolute Maximum Ratings
Table 4. General Specifications
PCLK, PCLK
TCLK
EXT_FB
REF_SEL
FSELA
FSELB
FSELC
FSELD
OE
QA
QB
QC0, QC1
QD0 – QD4
V
V
GND
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
Symbol
Symbol
CCA
CC
V
HBM
V
I
C
V
MM
V
C
OUT
T
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated
conditions is not implied.
LU
OUT
I
CC
IN
REF_SEL
PD
TT
IN
IN
Number
S
PLL_EN
Control
FSELA
FSELB
FSELC
FSELD
OE
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
Output Termination Voltage
ESD (Machine Model)
ESD (Human Body Model)
Latch-Up
Power Dissipation Capacitance
Input Capacitance
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Supply
Supply
Supply
Characteristics
Default
0
1
0
0
0
0
0
Characteristics
Name
Selects PCLK as reference clock
Test mode with PLL disabled. The input clock is
directly routed to the output dividers
Outputs enabled
QA = VCO ÷ 2
QB = VCO ÷ 4
QC = VCO ÷ 4
QD = VCO ÷ 4
(1)
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
V
V
Ground
CC
CC
2000
Min
200
200
Type
0
3
Differential clock reference
Low voltage positive ECL input
Single ended reference clock signal or test clock
Feedback signal input, connect to a QA, QB, QC, QD output
Selects input reference clock
Output A divider selection
Output B divider selection
Outputs C divider selection
Outputs D divider selection
Output enable/disable
Bank A clock output
Bank B clock output
Bank C clock outputs
Bank D clock outputs
Positive power supply for the PLL
Positive power supply for I/O and core
Negative power supply
–0.3
–0.3
–0.3
V
Min
–55
CC
Typ
4.0
10
÷ 2
Selects TCLK as reference clock
PLL enabled. The VCO output is routed to the
output dividers
Outputs disabled, PLL loop is open
VCO is forced to its minimum frequency
QA = VCO ÷ 4
QB = VCO ÷ 8
QC = VCO ÷ 8
QD = VCO ÷ 8
V
V
Description
CC
CC
Max
Max
±20
±50
150
4.6
+0.3
+0.3
1
Unit
Unit
mA
mA
°C
mA
pF
pF
V
V
V
V
V
V
Per output
Inputs
Condition
Condition
MPC9351
NETCOM
MPC9351
3