sy89809l Micrel Semiconductor, sy89809l Datasheet - Page 2

• Manufacturer Part Number: sy89809l
• Description: Sy89809l 3.3v 1 9 High-performance Low-voltage Bus Clock Driver
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
/LVPECL_CLK
M9999-092005
[e-mail] or [phone]
LVPECL_CLK
21, 19, 15, 13,
30, 28, 26, 22,
20, 18, 14, 12,
/HSTL_CLK
31, 29, 27, 23,
9, 16, 17, 24,
HSTL_CLK
PIN DESCRIPTION
PACKAGE/ORDERING INFORMATION
Pin Number
CLK_SEL
25, 32
VCCI
GND
2, 3
5, 6
11
10
OE
4
8
1
7
32-Pin TQFP (T32-1)
5
6
7
8
1
2
3
4
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
LVPECL_CLK,
/LVPECL_CLK
HSTL_CLK,
/HSTL_CLK
Pin Name
CLK_SEL
Top View
/Q0–/Q8
Q0–Q8
VCCO
VCCI
TQFP
T32-1
GND
OE
20
19
18
17
24
23
22
21
VCC Output
VCC Core
LVPECL
Ground
LVTTL
LVTTL
Output
Output
Power
Power
HSTL
HSTL
HSTL
Type
Input
Input
Input
Input
VCCO
Q4
/Q4
Q5
VCCO
Q3
/Q3
/Q5
Ordering Information
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
Part Number
SY89809LTC
SY89809LTCTR
SY89809LTH
SY89809LTHTR
Pin Function
Differential clock input selected by CLK_SEL. Can be left floating if not
selected. Floating input, if selected produces an indeterminate output. HSTL
input signal requires external termination 50 to GND.
Differential clock input selected by CLK_SEL. Can be left floating. Floating
input, if selected produces a LOW at the output (internal 75 pull-downs).
Requires external termination. 75k pull-up.
Selects HSTL_CLK input when LOW and LVPECL_CLK output when HIGH.
11k pull-up.
Enable input synchronized internally to prevent glitching of the Q0-Q8 and
/Q0-/Q8 outputs. Must be a minimum of three clock periods wide if
synchronous with the CLK inputs and must meet the t
(refer to AC Electrical Characteristics). If asynchronous, must be a minimum
of four clock periods wide. 11k pull-up.
Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and
LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated
with 50
output pairs may be left floating.
Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and
LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated
with 50
Unused output pairs may be left floating.
Core V
0.01 F low ESR capacitors as close to V
Output Buffer V
with 0.01 F low ESR capacitors as close to V
pins should be connected together on the PCB.
Ground.
CC
to GND. Q0–Q8 outputs are static LOW when OE = LOW. Unused
to GND. /Q0–/Q8 outputs are static HIGH when OE = LOW.
connected to 3.3V supply. Bypass with 0.1 F in parallel with
(3)
2
(2)
(2, 3)
CC
connected to 1.8V supply. Bypass with 0.1 F in parallel
Package
T32-1
T32-1
T32-1
T32-1
Type
(1)
Operating
Industrial
Industrial
Industrial
Industrial
Range
CCI
Pb-Free bar line indicator Pb-Free
Pb-Free bar line indicator Pb-Free
pin as possible.
CCO
SY89809LTH with
SY89809LTH with
SY89809LTC
SY89809LTC
pins as possible. All V
A
Package
Marking
= 25 C, DC Electricals only.
S
and t
H
Precision Edge®
requirements
SY89809L
NiPdAu
NiPdAu
Finish
CCO
Sn-Pb
Sn-Pb
Lead