sy89537l Micrel Semiconductor, sy89537l Datasheet - Page 17

• Manufacturer Part Number: sy89537l
• Description: Sy89537l 3.3v Precision Lvpecl And Lvds Programmable Multiple Output Bank Clock Synthesizer And Fanout Buffer
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
Output Bank and Frequency Control
There are five independently programmable output
frequency banks, four differential LVPECL output
banks and one differential LVDS output bank with
three output pairs. Each bank has frequency control
SELx and Enx to generate different divider ratios (see
“PECL and LVDS Output and Frequency Select”
Tables). It can be programmed for pass-through,
internal divided VCO clock divide-by- /2, /8 or disable
state. When disabled, the non-inverted output goes to
static LOW and the inverted output goes to static
HIGH.
Output Logic Characteristics
See “Output Termination Recommendations” for
proper termination. When LVPECL single-ended
output is desired, the unused complimentary output
should be terminated. Unused LVPECL output pairs
can be left floating. LVDS output pairs should be
terminated with 100Ω across the pair. In order to
minimize jitter and skew, unused LVDS output banks
and unused LVDS output pairs should be terminated
with 100Ω across each pair.
LVPECL Outputs:
LVDS Outputs:
Output Termination Recommendations
LVPECL
LVPECL has high input impedance, very low output
(open emitter) impedance, and small signal swing
which results in low EMI. LVPECL is ideal for driving
50Ω-and-100Ω-controlled impedance transmission
lines. There are several techniques for terminating the
LVPECL output: Parallel Termination Thevenin-
Equivalent, Parallel Termination (3-resistor), and AC-
coupled termination. Unused output pairs may be left
floating. However, single-ended outputs must be
terminated, or balanced.
December 2007
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Typical voltage swing is 800mV into 50Ω.
Common mode voltage is V
Typical voltage swing is 325mV into 100Ω.
Common mode voltage is 1.2V.
CCO
–1.3V.
17
LVDS
LVDS specifies a small swing of 325mV typical, on a
nominal 1.2V common mode above ground. The
common mode voltage has tight limits to permit large
variations in ground between an LVDS driver and
receiver. Also, change in common mode voltage, as a
function of data input, is kept to a minimum, to keep
EMI low.
Figure 13b. LVDS Common Mode Measurement
Figure 13a. LVDS Differential Measurement
Figure 12a. Parallel Thevenin-Equivalent
Figure 12b. Parallel Termination
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