sy89200u Micrel Semiconductor, sy89200u Datasheet - Page 5

• Manufacturer Part Number: sy89200u
• Description: Sy89200u Ultra-precision 1 8 Lvds Fanout With Three ?1/?2/?4 Clock Divider Output Banks
• Manufacturer: Micrel Semiconductor

LVDS OUTPUT DC Electrical Characteristics
V
AC Electrical Characteristics
V
Notes:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
8. Measured with 100mV input swing. See “Timing Diagram” section for definition of parameters. High-frequency AC-parameters are guaranteed by
9. Within-bank is the difference in propagation delays among the outputs within the same bank.
10. Bank-to-bank skew is the difference in propagation delays between outputs from difference banks. Bank-to-bank skew is also the phase offset
11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
12. RJ is measured with a K28.7 comma detect character pattern.
13. Total jitter definition: with an ideal clock input of frequency ≤f
14. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T
Micrel, Inc.
Symbol
V
V
V
V
V
∆V
Symbol
f
t
t
t
Tempco
t
t
t
August 2007
CC
CC
MAX
PD
RR
PD
SKEW
JITTER
f
, t
OH
OL
OUT
DIFF_OUT
OCM
design and characterization.
between each bank after MR is applied.
respective inputs.
specified peak-to-peak jitter value.
signal.
OCM
f
= 2.5V ±5%; T
= 2.5V ±5%; T
Parameter
Output HIGH Voltage; (Q, /Q)
Output LOW Voltage; (Q, /Q)
Output Voltage Swing; (Q, /Q)
Differential Output Voltage Swing
|Q – /Q|
Output Common Mode Voltage
(Q, /Q)
Change in Common Mode Voltage
(Q, /Q)
Parameter
Maximum Operating Frequency
Differential Propagation Delay
Reset Recovery Time
Differential Propagation Delay
Temperature Coefficient
Within-Bank Skew
Bank-to-Bank Skew
Bank-to-Bank Skew
Part-to-Park Skew
Random Jitter (RJ)
Total Jitter (TJ)
Cycle-to-Cycle Jitter
Rise/Fall Time
A
A
= –40°C to +85°C; R
= –40°C to +85°C; R
(8)
L
L
= 100Ω across Q and /Q, unless otherwise stated.
= 100Ω across all outputs (Q and /Q), unless otherwise stated.
Condition
Condition
V
IN-to-Q
/MR-to-Q
/MR(L-H)-to-(L-H)
Within same fanout bank, Note 9
Same divide setting, Note 10
Differential divide setting, Note 10
Note 11
Note 12
Note 13
Note 14
20% to 80% at full output swing
OUT
>200mV
MAX
, no more than one output edge in 10
(7)
5
n
– T
n-1
where T is the time between rising edges of the output
Clock
12
[e-mail]
output edges will deviate by more than the
1.125
0.925
Min
Min
250
500
–50
500
1.5
40
Typ
Typ
700
350
700
115
10
15
25
80
or [phone]
M9999-082407-E
1.475
1.275
Max
Max
+50
900
900
900
200
150
35
50
10
25
1
1
SY89200U
Units
Units
ps
ps
fs/°C
GHz
ps
mV
mV
mV
ps
ps
ps
ps
ps
ps
ps
ps
V
V
V
RMS
RMS
PP