sy87700l Micrel Semiconductor, sy87700l Datasheet - Page 3

• Manufacturer Part Number: sy87700l
• Description: Sy87700l 3.3v 32-175mbps Anyrate Clock And Data Recovery
• Manufacturer: Micrel Semiconductor

M9999-111406
[e-mail] or [phone]
Micrel, Inc.
Note:
1. V
Pin Number
PIN DESCRIPTIONS
CC
20, 23
13, 14
SOIC
27
26
17
25
24
22
21
19
18
11
12
16
15
10
, V
4
5
7
6
8
9
3
2
1
CCA
, V
CCO
Pin Number
must be the same value.
27, 28,
TQFP
29, 30
19, 22
12, 13
1, 8
26
32
25
16
31
24
23
21
20
18
17
10
15
14
2
3
5
4
6
7
9
FREQSEL1,
FREQSEL2,
FREQSEL3
Pin Name
DIVSEL1,
RDOUTP,
RDOUTN
DIVSEL2
REFCLK
CLKSEL
RCLKP,
RDINP,
TCLKP,
PLLSP,
PLLRP,
TCLKN
RDINN
RCLKN
PLLRN
PLLSN
V
V
LFIN
GND
V
CD
NC
CCA
CCO
CC
Pin Function
Serial Data Input (Differential PECL): These built-in line receiver inputs are
connected to the differential receive serial data stream. An internal receive
PLL recovers the embedded clock (RCLK) and data (RDOUT) information.
The incoming data rate can be within one of five frequency ranges depend-
ing on the state of the FREQSEL pins. See “Frequency Selection” table.
Reference Clock (TTL Inputs): This input is used as the reference for the
internal frequency synthesizer and the “training” frequency for the receiver
PLL to keep it centered in the absence of data coming in on the RDIN inputs.
Carrier Detect (PECL Input): This input controls the recovery function of the
Receive PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When this input is
HIGH the input data stream (RDIN) is recovered normally by the Receive
PLL. When this input is LOW the data on the inputs RDIN will be internally
forced to a constant LOW, the data outputs RDOUT will remain LOW, the
Link Fault Indicator output LFIN forced LOW and the clock recovery PLL
forced to look onto the clock frequency generated from REFCLK.
Frequency Select (TTL Inputs): These inputs select the output clock
frequency range as shown in the “Frequency Selection” table.
Divider Select (TTL Inputs): These inputs select the ratio between the
output clock frequency (RCLK/TCLK) and the REFCLK input frequency as
shown in the “Reference Frequency Selection” table.
Clock Select (TTL Inputs): This input is used to select either the recovered
clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency
synthesizer (CLKSEL = LOW) to the TCLK outputs.
Link Fault Indicator (TTL Output): This output indicates the status of the
input data stream RDIN. Active HIGH signal is indicating when the internal
clock recovery PLL has locked onto the incoming data stream. LFIN will go
HIGH if CD is HIGH and RDIN is within the frequency range of the Receive
PLL (1000ppm). LFIN is an asynchronous output.
Receive Data Output (Differential PECL): These ECL 100k outputs
represent the recovered data from the input data stream (RDIN). This
recovered data is specified against the rising edge of RCLK.
Clock Output (Differential PECL): These ECL 100k outputs represent the
recovered clock used to sample the recovered data (RDOUT).
Clock Output (Differential PECL): These ECL 100k outputs represent
either the recovered clock (CLKSEL = HIGH) used to sample the recovered
data (RDOUT) or the transmit clock of the frequency synthesizer
(CLKSEL = LOW).
Clock Synthesis PLL Loop Filter. External loop filter pins for the clock
synthesis PLL.
Clock Recovery PLL Loop Filter. External loop filter pins for the receiver
PLL.
Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Ground
No Connect
3
(1)
(1)
(1)
SY87700L