mc100ep51d ON Semiconductor, mc100ep51d Datasheet - Page 2

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mc100ep51d

Manufacturer Part Number
mc100ep51d
Description
3.3v / 5v Ecl D Flip-flop With Reset And Differential Clock
Manufacturer
ON Semiconductor
Datasheet

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RESET
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
CLK
CLK
D
1
2
3
4
Table 3. ATTRIBUTES
1. For additional information, see Application Note AND8003/D.
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
D
Flip-Flop
R
Characteristics
8
7
6
5
http://onsemi.com
Oxygen Index: 28 to 34
Charged Device Model
V
Q
Q
V
CC
EE
Human Body Model
Machine Model
2
TSSOP−8
* Pins will default LOW when left open.
SOIC−8
Z = LOW to HIGH Transition
CLK*, CLK*
Reset*
D*
Q, Q
V
V
Table 1. PIN DESCRIPTION
PIN
DFN8
EP
Table 2. TRUTH TABLE
CC
EE
D
H
X
L
Pb Pkg
Level 1
Level 1
Level 1
UL 94 V−0 @ 0.125 in
R
H
L
L
ECL Clock Inputs
ECL Asynchronous Reset
ECL Data Input
ECL Data Outputs
Positive Supply
Negative Supply
FUNCTION
(DFN8 only) Thermal exposed
pad must be connected to a suf-
ficient thermal conduit. Electric-
ally connect to the most negative
supply (GND) or leave uncon-
nected, floating open.
165 Devices
> 200 V
> 2 kV
> 2 kV
Value
75 kW
N/A
Pb−Free Pkg
CLK
Level 1
Level 3
Level 1
X
Z
Z
Q
H
L
L

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