mc88915 Integrated Device Technology, mc88915 Datasheet - Page 12

• Manufacturer Part Number: mc88915
• Description: Low Skew Cmos Pll Clock Driver
• Manufacturer: Integrated Device Technology

IDT™ / ICS™ CMOS PLL CLOCK DRIVERS
MC88915
LOW SKEW CMOS PLL CLOCK DRIVERS
MC88915 SYSTEM LEVEL TESTING FUNCTIONALITY
88915 is in low frequency “test mode”. In test mode (with
FREQ_SEL high), the 2X_Q output is inverted from the
selected SYNC input, and the “Q” outputs are divide-by-2
(negative edge triggered) of the SYNC input, and the Q/2
output is divide-by-4. With FREQ_SEL low the 2X_Q output
is divide-by-2 of the SYNC, the “Q” outputs divide-by-4, and
the Q/2 output divide-by-8. These relationships can be seen
on the block diagram. A recommended test configuration
When the PLL_EN pin is low, the VCO is disabled and the
Figure 9. Representation of a Potential Multi-Processing Application Utilizing the MC88915
SYSTEM
CLOCK
SOURCE
AT POINT OF USE
for Frequency Multiplication and Low Board-to-Board Skew
DISTRIBUTE
CLOCK @ f
CLOCK @ 2f
CLOCK
@ f
MC88915
MC88915
PLL
PLL
MEMORY
CARDS
MC88915T
2f
2f
PLL
12
2f
would be to use SYNC0 as the test clock input, and tie
PLL_EN and REF_SEL together and connect them to the test
select logic. When these inputs are low, the 88915 is in test
mode and the SYNC0 input is selected.
run at 1 MHz or below, and the 88915 cannot lock onto that
low of an input frequency. In the test mode described above,
any frequency test signal can be used.
CMMU
CMMU
CMMU
CMMU
This functionality is needed since most board-level testers
CPU
CPU
CONTROL
MEMORY
AT POINT OF USE
CLOCK @ 2f
CMMU
CMMU
CMMU
CMMU
CMMU
CMMU
CARD
CARD
CPU
CPU
MC88915 REV 6 JULY 10, 2007