mc88920 Integrated Device Technology, mc88920 Datasheet - Page 4

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mc88920

Manufacturer Part Number
mc88920
Description
Low Skew Cmos Pll Clock Drivers With Power-down/power-up Feature
Manufacturer
Integrated Device Technology
Datasheet

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IDT™ Low Skew CMOS PLL Clock Drivers With Power-Down/Power-up Feature
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88920
Low Skew CMOS PLL Clock Drivers With Power-Down/Power-up Feature
MC88920
SYNC INPUT TIMING REQUIREMENTS
FREQUENCY SPECIFICATIONS (T A = 0 C to 70 C; V CC = 5.0V
1. Maximum Operating Frequency is guaranteed with the 88920 in a phase–locked condition, and all outputs loaded at 50pF.
MOTOROLA
t RISE/FALL
SYNC Input
t CYCLE ,
SYNC Input
Duty Cycle
Fmax (2X_Q)
Fmax (‘Q’)
PLL_EN
Symbol
RST_IN
SYNC1
Symbol
MR
Maximum Operating Frequency, 2X_Q Output
Maximum Operating Frequency,
Q0–Q2, Q3 Outputs
POWER–ON
RESET
Rise/Fall Time, SYNC Input
From 0.8V to 2.0V
Input Clock Period
SYNC Input
Duty Cycle, SYNC Input
RESET_OUT 1024 CYCLE
LOCK INDICATOR AND
PFD
COUNT CIRCUITRY
0
Freescale Semiconductor, Inc.
For More Information On This Product,
1
PUMP
CH
Figure 1. MC88920 Logic Block Diagram
Parameter
RC1
Parameter
Go to: www.freescale.com
VCO
2
4
4
5%)
D
D
D
D
D
D
R
R
R
R
R
R
Q
Q
Q
Q
Q
Q
Q
Minimum
f 2X_Q 4
Guaranteed Minimum
1
50%
“Dummy” Flip–Flop to Maintain
Phase–Locked Operation
50
25
25%
Maximum
Q0
Q1
Q2
Q3
Q/2
200
TIMING SOLUTIONS
5.0
RST_OUT
2X_Q
BR1333 — REV 5
Unit
ns
ns
MHz
MHz
Unit
NETCOM
MC88920

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