nb6l295 ON Semiconductor, nb6l295 Datasheet

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nb6l295

Manufacturer Part Number
nb6l295
Description
Lvpecl Dual Programmable Delay
Manufacturer
ON Semiconductor
Datasheet

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NB6L295
2.5V / 3.3V Dual Channel
Programmable Clock/Data
Delay with Differential
LVPECL Outputs
Multi-Level Inputs w/ Internal Termination
designed primarily for Clock or Data de-skewing and timing
adjustment. The NB6L295 is versatile in that two individual variable
delay channels, PD0 and PD1, can be configured in one of two
operating modes, a Dual Delay or an Extended Delay.
section which is designed using a matrix of gates and a chain of
multiplexers. There is a fixed minimum delay of 3.2 ns per channel.
plus PD1 and is accomplished with the Serial Data Interface MSEL bit
set High. This will internally cascade the output of PD0 into the input
of PD1. Therefore, the Extended Delay path starts at the IN0/IN0
inputs, flows through PD0, cascades to the PD1 and outputs through
Q1/Q1. There is a fixed minimum delay of 6 ns for the Extended
Delay Mode.
channel via a 3-pin Serial Data Interface, described in the application
section. The digitally selectable delay has an increment resolution of
typically 11 ps with a net programmable delay range of either 0 ns to
6 ns per channel in Dual Delay Mode; or from 0 ns to 11.2 ns for the
Extended Delay Mode.
LVPECL, LVDS or CML logic levels; or by single ended LVPECL,
LVCMOS or LVTTL. A single enable pin is available to control both
inputs. The SDI input pins are controlled by LVCMOS or LVTTL
level signals. The NB6L295 LVPECL output contains temperature
compensation circuitry. This device is offered in a 4 mm x 4 mm
24-pin QFN Pb-free package. The NB6L295 is a member of the
ECLinPS MAX™ family of high performance products.
© Semiconductor Components Industries, LLC, 2007
November, 2007 - Rev. 0
The NB6L295 is a Dual Channel Programmable Delay Chip
In the Dual Delay Mode, each channel has a programmable delay
The Extended Delay Mode amounts to the additive delay of PD0
The required delay is accomplished by programming each delay
The Multi-Level Inputs can be driven directly by differential
Input Clock Frequency > 1.5 GHz with 550 mV
V
Input Data Rate > 2.5 Gb/s
Programmable Delay Range: 0 ns to 6 ns per Delay
Channel
Programmable Delay Range: 0 ns to 11.2 ns for
Extended Delay Mode
Total Delay Range: 3.2 ns to 8.8 ns per Delay Channel
Total Delay Range: 6 ns to 17 ns in Extended Delay
Mode
Monotonic Delay: 11 ps Increments in 511 Steps
Linearity $20 ps, Maximum
100 ps Typical Rise and Fall Times
OUTPP
1
3 ps Typical Clock Jitter, RMS
20 ps Pk-Pk Typical Data Dependent Jitter
LVPECL, CML or LVDS Differential Input Compatible
LVPECL, LVCMOS, LVTTL Single Ended Input
Compatible
3-Wire Serial Interface
Operating Range: V
LVPECL Output Level; 780 mV Peak-to-Peak, Typical
Internal 50 W Input Termination Provided
-40°C to 85°C Ambient Operating Temperature
24-Pin QFN, 4 mm x 4 mm
These are Pb-Free Devices
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
24
*For additional marking information, refer to
Application Note AND8002/D.
A
L
Y
W
G
(Note: Microdot may be in either location)
1
ORDERING INFORMATION
CC
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
http://onsemi.com
= 2.375 V to 3.6 V
MN SUFFIX
CASE 485L
QFN-24
Publication Order Number:
1
DIAGRAM*
MARKING
24
ALYWG
NB6L295/D
NB6L
295
G

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nb6l295 Summary of contents

Page 1

... The SDI input pins are controlled by LVCMOS or LVTTL level signals. The NB6L295 LVPECL output contains temperature compensation circuitry. This device is offered 24-pin QFN Pb-free package. The NB6L295 is a member of the ECLinPS MAX™ family of high performance products. • ...

Page 2

... NB6L295 Figure 1. Simplified Functional Block Diagram http://onsemi.com 2 ...

Page 3

... VCC1s are connected to each other: VCC0 and VCC1 are separate. NB6L295 VT0 IN0 IN0 VT0 GND VCC0 NB6L295 VT1 IN1 IN1 VT1 GND VCC1 Figure 2. Pinout: QFN-24 (Top View) Positive Supply Voltage for the Inputs and Core Logic Input Enable/ Disable for both PD0 and PD1 ...

Page 4

... Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. NB6L295 Characteristics Human Body Model Machine Model ...

Page 5

... IH IL,, ISE single-ended mode and V parameters must be complied with simultaneously. IHD ILD, ID CMR 9. V (min) varies 1:1 with voltage on GND Pin, V CMR of the differential input signal. NB6L295 CC0 and Outputs Open) (Sum 3 CC0 CC1 ...

Page 6

... Deviation from a linear delay (actual Min to Max) in the Dual Mode 511 programmable steps. 13. Additive random CLOCK jitter with 50% duty cycle input clock signal. 14. NRZ data at PRBS23 and K28.5. 15. Input and output voltage swing is a single-ended measurement operating in differential mode. NB6L295 = 2.375 V to 3.6 V, GND = ...

Page 7

... Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. NB6L295 = 2.375 V to 3.6 V, GND = -40° ...

Page 8

... Serial Data Interface Programming The NB6L295 is programmed by loading the 11-Bit SHIFT REGISTER using the SCLK, SDATA and SLOAD inputs. The 11 SDATA bits are 1 PSEL bit, 1 MSEL bit and 9 delay value data bitsD[8:0]. A separate 11-bit load cycle is required to program the delay data value of each channel, PD0 and PD1. For example, at powerup two load cycles will be needed to initially set PD0 and PD1 ...

Page 9

... SDI programming, then pulled HIGH (disabled) during programming. After programming, the EN should be returned LOW (enabled) for functional delay operation. EN LSB PSEL MSEL D0 SDIN SCLK C0 C1 SLOAD t SDIN to s SCLK t SDIN to SCLK h NB6L295 Q0/Q0 MSEL 0 1 11-Bit Shift Register Figure 8. SDI Timing Diagram http://onsemi.com 9 ...

Page 10

... NB6L295 (Decimal) MSEL (0) 0 (1) 0 (2) 0 (3) 0 (4) 0 (5) 0 (6) 0 (7) 0 (8) 0 • • • (16) ...

Page 11

... Driven Differentially IHD(MAX) V ILD(MAX) V IHD CMR ID V ILD V IHD(MIN) V ILD(MIN) GND Figure 14. V Diagram CMR NB6L295 VTx INx I INx 50 W VTx Figure 9. Input Structure thmax thmin GND INx INx Figure 13. Differential Inputs Driven INx INx ...

Page 12

... GND GND Single-Ended Driver GND GND Figure 20. Capacitor-Coupled Single-Ended ; Interface (V Bypassed to Ground with 0.1 mF Capacitor) V REFAC http://onsemi.com INx NB6L295 = INx GND Figure 17. LVDS Interface CC V ...

Page 13

... Figure 22. Output Voltage Amplitude (V Output Frequency at Ambient Temperature (Typical) ORDERING INFORMATION Device NB6L295MNG NB6L295MNTXG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NB6L295 ...

Page 14

... FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A2 0.60 0.80 A3 0.20 REF b 0.23 0.28 D 4.00 BSC D2 2.70 2.90 E 4.00 BSC E2 2.70 2.90 e 0.50 BSC L 0.35 0.45 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NB6L295/D ...

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