nb6lq572 ON Semiconductor, nb6lq572 Datasheet

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nb6lq572

Manufacturer Part Number
nb6lq572
Description
2.5v / 3.3v Differential 4 1 Mux W/input Equalizer To 1 2 Lvpecl Clock/data Fanout / Translator
Manufacturer
ON Semiconductor
Datasheet

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Part Number:
nb6lq572MNR4G
Manufacturer:
ON Semiconductor
Quantity:
250
NB6LQ572
2.5V / 3.3V Differential 4:1
Mux w/Input Equalizer to
1:2 LVPECL Clock/Data
Fanout / Translator
Multi−Level Inputs w/ Internal Termination
input multiplexer and a 1:2 LVPECL Clock / Data fanout buffer that
operates up to 5 GHz / 6.5 Gbps respectively with a 2.5 V or 3.3 V
power supply.
which when placed in series with a Clock / Data path, will enhance the
degraded signal transmitted across an FR4 backplane or cable
interconnect. For applications that do not require Equalization,
consider the NB6L572, which is pin−compatible to the NB6LQ572.
resistors and will accept differential LVPECL, CML, or LVDS logic
levels. The NB6LQ572 incorporates a pair of Select pins that will
choose one of four differential inputs and will produce two identical
LVPECL output copies of Clock or Data. As such, the NB6LQ572 is
ideal for SONET, GigE, Fiber Channel, Backplane and other
Clock/Data distribution applications.
externally loaded and terminated with a 50 W resistor to V
and are optimized for low skew and minimal jitter.
Pb−Free package. Application notes, models, and support
documentation are available at www.onsemi.com.
high performance clock products.
Features
© Semiconductor Components Industries, LLC, 2009
April, 2009 − Rev. 0
The NB6LQ572 is a high performance differential 4:1 Clock/Data
Each INx/INx input pair incorporates a fixed Equalizer Receiver,
The differential Clock / Data inputs have internal 50 W termination
The two differential LVPECL outputs will swing 750 mV when
The NB6LQ572 is offered in a low profile 5x5 mm 32−pin QFN
The NB6LQ572 is a member of the ECLinPS MAX™ family of
Input Data Rate > 6.5 Gb/s Typical
Data Dependent Jitter < 10 ps
Maximum Input Clock Frequency > 5 GHz Typical
Random Clock Jitter < 0.8ps RMS
Fixed Input Equalization
Low Skew 1:2 LVPECL Outputs, < 15 ps max
4:1 Multi−Level Mux Inputs, accepts LVPECL, CML LVDS
150ps Typical Propagation Delay
55ps Typical Rise and Fall Times
Differential LVPECL Outputs, 800 mV peak−to−peak, typical
Operating Range: V
Internal 50 W Input Termination Resistors
V
QFN−32 Package, 5mm x 5mm
−40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices
REFAC
Reference Output
CC
= 2.375 V to 3.6 V
CC
1
– 2 V
See detailed ordering and shipping information on page 9 of
this data sheet.
CASE 488AM
MN SUFFIX
(Note: Microdot may be in either location)
QFN32
1
ORDERING INFORMATION
A
WL
YY
WW
G
32
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Publication Order Number:
1
AWLYYWWG
MARKING
DIAGRAM
NB6L
Q572
G
NB6LQ572/D

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nb6lq572 Summary of contents

Page 1

... LVPECL, CML, or LVDS logic levels. The NB6LQ572 incorporates a pair of Select pins that will choose one of four differential inputs and will produce two identical LVPECL output copies of Clock or Data. As such, the NB6LQ572 is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. ...

Page 2

Multilevel Inputs LVPECL, LVDS, CML IN0 50 W VT0 50 W IN0 VREFAC0 IN1 50 W VT1 50 W IN1 VREFAC1 IN2 50 W VT2 50 W IN2 VREFAC2 IN3 50 W VT3 50 W IN3 VREFAC3 ...

Page 3

Table 2. PIN DESCRIPTION Pin Num- ber Pin Name I IN0, IN0 LVPECL, CML IN1, IN1 LVDS Input 25, 28 IN2, IN2 29, 32 IN3, IN3 2, 6 VT0, VT1 26, 30 VT2, VT3 15 SEL0 ...

Page 4

Table 3. ATTRIBUTES ESD Protection R − SELx Input Pull−up Resistor PU Moisture Sensitivity (Note 3) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM ...

Page 5

Table 5. DC CHARACTERISTICS POSITIVE LVPECL OUTPUT (Note 5) Symbol Characteristic POWER SUPPLY V Power Supply Voltage CC I Power Supply Current for LVPECL OUTPUTS V Output HIGH Voltage (Note Output LOW Voltage (Note ...

Page 6

Table 6. AC CHARACTERISTICS V Symbol f Maximum Input Clock Frequency MAX f Maximum Operating Data Rate DATAMAX f Maximum Toggle Frequency, SELx SEL V Output Voltage Amplitude (@ V OUTPP t , Propagation Delay to Differential Outputs PLH t ...

Page 7

V CC INx 50 W VTx 50 W INx Figure 4. Input Structure IHmax V thmax V ILmax Vth IHmin V thmin V ILmin V EE Figure 6. V ...

Page 8

... V − 2 http://onsemi.com NB6LQ572 OPEN CLKx GND GND Figure 13. LVDS Interface V CC NB6LQ572 REFAC GND Connected to External V T REFAC D Receiver Device D ) ...

Page 9

... Q Driver Q DJ1 Figure 17. Typical NB6LQ572 Equalizer Application and Interconnect with PRBS23 Pattern at 6.5 Gbps DEVICE ORDERING INFORMATION Device NB6LQ572MNG NB6LQ572MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ...

Page 10

... D 5.00 BSC D2 2.950 3.100 3.250 E 5.00 BSC E2 2.950 3.100 3.250 e 0.500 BSC K 0.200 −−− −−− L 0.300 0.400 0.500 5.30 3.20 3.20 5. 0.50 PITCH ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB6LQ572/D ...

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