w83195bg-912 Winbond Electronics Corp America, w83195bg-912 Datasheet
w83195bg-912
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w83195bg-912 Summary of contents
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... W83195BG-912 Winbond Clock Generator For VIA P4/KT Series Chipset Date: Mar/22/2006 Revision: 0.6 ...
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... CLOCK GEN. FOR VIA P4/KT SERIES CHIPSET W83195BG-912 Data Sheet Revision History PAGES DATES VERSION 1 2 n.a. 11/01/04 3 n.a. 03/22/ Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. ...
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... Register 12: Control (Default: 3Ch) .......................................................................................14 7.14 Register 13: Control (Default: 24h) ........................................................................................15 7.15 Register 14: Control (Default: 5Xh)........................................................................................15 7.16 Register 15: Slew Rate Control (Default: 55h) ......................................................................15 7.17 Register 16: DRAM Buffer Control (1 = Enable Disable) (Default: 7Fh).......................16 7.18 Register 17: Slew Rate Control (Default: CFh) .....................................................................16 7.19 Register 18: M/N Time & Type Control (Default: 5Bh)..........................................................17 7.20 Register 19: Reserved ...........................................................................................................17 W83195BG-912 - II - ...
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... CPU 0.7V Electrical Characteristics ......................................................................................21 9.5 CPU 1.0V Electrical Characteristics ......................................................................................21 9.6 AGP Electrical Characteristics ...............................................................................................22 9.7 PCI Electrical Characteristics.................................................................................................22 9.8 24M, 48M Electrical Characteristics ......................................................................................22 9.9 REF Electrical Characteristics ...............................................................................................23 10. ORDERING INFORMATION..................................................................................................... 23 11. HOW TO READ THE TOP MARKING...................................................................................... 24 12. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 25 W83195BG-912 Publication Release Date: Mar. 2006 - III - Revision 0.6 ...
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... The W83195BG-912 provides I each clock outputs and provides +/-0.25%, +/-0.5% center type and –0.5%, -1.0% down type spread spectrum or programmable S.S.T. scale to reduce EMI. The W83195BG-912 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. 2. PRODUCT FEATURES • 1 pairs differential clock for CPU (P4 or Athlon) • ...
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... VDD48 VDD GND 25 32 IREF 26 31 SCLK SDATA W83195BG-912 VTT_PWRGD#/REF1 VDDR GND CPUT/CPUOD_T CPUC/CPUOD_C VDDC VDDI CPUCS_C CPUCS_T GND FBOUT BUF_IN DDRT0 DDRC0 DDRT1 DDRC1 VDDD GND DDRT2 DDRC2 DDRT3 DDRC3 VDDD GND DDRT4 ...
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... PLL2 Divider XTAL OSC PLL1 VCOCLK Spread Spectrum M/N/Ratio ROM Divider Latch &POR Control Logic &Config Register I2C Interface Publication Release Date: Mar. 2006 - 3 - W83195BG-912 FBOUT 6 DDRT(0:5) DDRC(0:5) 6 48MHz 24_48MHz 2 REF 0:1 CPUT/CPUOD_T CPUC/CPUOD_C CPUCS_T CPUCS_C 3 AGP (0:2) PCI_F 6 PCI 1:6 RESET# Rref Revision 0.6 ...
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... OUT 2.5V differential clock outputs for Chipset. OUT 3.3V 66MHz clock output IN Power up Latched input to selecting pin 53,52 and 56 output tp120k type, SELP4_K7=1 the 53, Mode and pin 56 is VTT_PWRGD#, SELP4_K7=0 the 53, Mode and pin 56 is REF1.This is internal 120KΩ pull up. OUT 3.3V 66MHz clock output W83195BG-912 DESCRIPTION DESCRIPTION ...
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... This is internal 120KΩ pull up. OUT 24MHz clock output Latched input for FS2 at initial power up for H/W selecting the td120k output frequency clocks. This is internal 120KΩ pull down W83195BG-912 DESCRIPTION DESCRIPTION Publication Release Date: Mar. 2006 Revision 0.6 ...
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... Select by register 1 bit 6 L_MODE if L_MODE=1 this pin is System reset signal when the watchdog is time out. This pin will generate 250mS when the watchdog timer is timeout Select by register 1 bit 6 L_MODE if L_MODE=0 this pin is Power Down Function. This is internal 120KΩ pull up W83195BG-912 DESCRIPTION DESCRIPTION Reference R, Output Ioh @ Z Current Ioh=6*Iref 0 ...
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... PWR 3.3V power supply analog core. VDDD PWR 3.3V or 2.5V power for DRAM buffer part. VDDI PWR 2.5V power supply for CPUCS_T/C. VDDC PWR 3.3V power supply for CPUT/C. VDDR PWR 3.3V power supply for REF GND PWR Ground pin for 3 W83195BG-912 DESCRIPTION Publication Release Date: Mar. 2006 Revision 0.6 ...
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... W83195BG-912 AGP (MHZ) PCI (MHZ) 66.8 33.4 66.6 33.3 60.1 30.0 66.6 33.3 72.0 36.0 70.1 35.0 64.0 32.0 70.1 35.0 66.6 33.3 66.6 33.3 66.6 33.3 66.6 33.3 66.6 33.3 66.6 33.3 66.6 33.3 66.6 33.3 80.1 40.0 82.0 41.0 66.6 33.3 67.9 34.0 70.0 35.0 72.1 36.1 73.9 37.0 76.0 38.0 66.8 33.4 67.3 33.6 66.8 33.4 66.8 33.4 66.6 33.3 66.6 33.3 66.6 33.3 66.6 33.3 ...
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... Pin 53,52 CPUT/C output control Mapping software table. Power on latched value of FS3 (20) pin. Power on latched value of FS2 (21) pin. Power on latched value of FS1 (10) pin. Power on latched value of FS (1) pin W83195BG-912 2 C Default 1 (Read only) Default 0 (Read only) Default 0 (Read only) Default 1 (Read only) Publication Release Date: Mar ...
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... Default value follow hardware trapping data on SEL24_48# pin. Program this bit => 1: Enable Watchdog Timer feature. 0: Disable Watchdog Timer feature. Read-back this bit => During timer count down the bit read back count to zero, this bit read back W83195BG-912 TYPE R/W R/W ...
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... M_DIV [0] 1 DESCRIPTION Read Back only. Timeout Flag. This bit is Read Only. 1: Watchdog has ever started and counts to zero. 0: Watchdog is restarted and counting. These bits will be reloaded in Reg-0 to select frequency table. As the watchdog is timeout and EN_SAFE_FREQ=1. DESCRIPTION FUNCTION DESCRIPTION - 11 - W83195BG-912 TYPE R R/W TYPE R/W R/W R/W R/W R/W R/W ...
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... Spread Spectrum Down Counter bit 3 ~ bit 0 2’s complement representation. Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000 PWD Function Description 0 Programmable N divisor value bit 9 0 Refer to Table-2 0 BUF_IN to FBOUT skew control. 0 300ps/per stage 0 0 Define the CPU/AGP/PCI divider ratio Refer to Table W83195BG-912 ...
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... FUNCTION DESCRIPTION 0: Output frequency depend on frequency table 1: Program all clock frequency by changing M/N value The equation is VCO =14.318MHz*(N+4)/ M. BUF_IN to OUT skew control. 300ps/per stage Charge pump current selection - 13 - W83195BG-912 PIN8 PIN18 AGP2 PCI6 PCI_STOP# CLK_STOP# AGP2 PCI6 AGP2 PCI6 AGP ...
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... Default, 1: Inverse 0 Tri-state all output if set 1 1 Spread spectrum implementation method 1 : Pendulum type 0 : Original 1 Spread Spectrum type select. 00: Down 1% 1 01: Down 0.5% 10: Center ± 0.5% 11: Center ± 0.25% 1 CPU to AGP skew control, Skew resolution is 340ps Expand the skew direction is same as 0 CPU_AGP_SKEW [2:0] setting W83195BG-912 ...
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... Strong , 00 : Weak , 10/01 : Normal Device active mode selection 1: P4 mode 0: K7 mode Default value follow hardware SELP4_K7/AGP1 (Default 1) Inverse feature 1: inverse DDROUT/FBOUT clock 0: Normal (Default 0) FUNCTION DESCRIPTION PCI_F slew rate control 11: Strong, 00: Weak, 10/01: Normal - 15 - W83195BG-912 trapping data on pin7 Publication Release Date: Mar. 2006 Revision 0.6 ...
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... DDRT1, DDRC1 output control DDRT0, DDRC0 output control FUNCTION DESCRIPTION FBOUT slew rate control 11: Strong, 00: Weak, 10/01: Normal CPUODT/C slew rate control 11: Strong, 00: Weak, 10/01: Normal DDR3, 4,5/SDRAM6, 7,8,9,10,11 slew rate control 11: Strong, 00: Weak, 10/01: Normal DDR0, 1,2/SDRAM 0,1,2,3,4,5 slew rate control 11: Strong, 00: Weak, 10/01: Normal - 16 - W83195BG-912 ...
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... M/N mode M value change time control Reserved for Winbond internal use, don’t modify it Reserved for Winbond internal use, don’t modify it M_DIVIDER OR N_DIVIDER TIMING COUNTER FUNCTION DESCRIPTION Winbond Chip ID. W83195BG-912. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. ...
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... MASK definition for code body *A****001: 01, *A****002: 10, *A****003: 11, MASK version definition for master body *A****001AA: 00, *A****001AB: 01, *A****001AC: 10, *A****001AD: 11. MASK version definition for code body *A****001A: 00, *A****001B: 01 *A****001C: 10, *A****001D W83195BG-912 *A****004:00 ...
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... Block Read and Block Write Protocol 8.1 Block Write protocol 8.2 Block Read protocol ## In block mode, the command code must filled 00H 8.3 Byte Write protocol 8.4 Byte Read protocol 2 C Serial Bus for microprocessor to read/write internal registers. In the - 19 - W83195BG-912 2 C Publication Release Date: Mar. 2006 Revision 0.6 ...
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... 350 mA dd Cin 5 pF Cout 6 pF Lin W83195BG-912 RATING -0.5V to +4. 4.6 V 3.135V to 3.465V 3.135V to 3.465V - 65° 150°C - 55° 125°C 0° 70°C 2000V ° ° +70 C, Cl=10pF TEST CONDITIONS dc dc All outputs using 3.3V power dc All outputs using 3.3V power ...
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... Mhz 175 700 ps 100 to 200Mhz 510 760 mV 100 to 200Mhz 150 ps 100 to 200Mhz 100 to 200Mhz - 21 - W83195BG-912 ° ° +70 C, Cl=10pF TEST CONDITIONS Measured at 1.5V Crossing point Measured at 1.5V Measured at 1.5V Measured at 1.5V Measured at 1.5V TEST CONDITIONS TEST CONDITIONS Publication Release Date: Mar. 2006 Revision 0.6 ...
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... Measure 1.5V point -33 mA Vout=1.0V -33 mA Vout=3.135V 30 mA Vout=1.95V 38 mA Vout=0. W83195BG-912 TEST CONDITIONS Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V TEST CONDITIONS Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V ...
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... Measure from 0.4V to 2.4V 1000 4000 ps Measure from 2.4V to 0.4V 1000 ps Measure 1.5V point -33 mA Vout=1.0V -33 mA Vout=3.135V 30 mA Vout=1.95V 38 mA Vout=0.4V PACKAGE TYPE 56 PIN SSOP - 23 - W83195BG-912 TEST CONDITIONS PRODUCTION FLOW Commercial, 0°C to +70°C Publication Release Date: Mar. 2006 Revision 0.6 ...
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... Tracking code 342 527: packages made in '2005, week 27 G: assembly house ID; O means OSE, G means GR A: Internal use code A: IC revision SA: Internal use code All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. W83195BG-912 - 24 - ...
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... SYMBOL .045 .055 A A1 END VIEW SEE DETAIL "A" θ θ DETAIL"A" W83195BG-912 DIMENSION IN MM DIMENSION IN INCH MIN. NOM MAX. MIN. NOM 2.41 2.57 2.79 0.095 0.101 0.30 0.41 0.20 0.008 0.012 0.090 2.34 0.088 2.24 2.29 0.010 0.20 0.25 0.34 ...
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... Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Important Notice - 26 - W83195BG-912 ...