cy7b994v-5ai Cypress Semiconductor Corporation., cy7b994v-5ai Datasheet
cy7b994v-5ai
Related parts for cy7b994v-5ai
cy7b994v-5ai Summary of contents
Page 1
... Cypress Semiconductor Corporation Document #: 38-07127 Rev. *F High-speed Multi-phase PLL Clock Buffer Functional Description The CY7B993V and CY7B994V High-speed Multi-phase PLL Clock Buffers offer user-selectable control over system clock functions. This multiple-output clock driver provides the system integrator with functions necessary to optimize the timing of high-performance computer and communication systems ...
Page 2
... Document #: 38-07127 Rev. *F 100-pin TQFP CY7B993/ RoboClock CY7B993V CY7B994V VCCQ 74 REFA+ 73 REFA – 72 REFSEL 71 REFB– 70 REFB+ 69 2F0 GND 66 2QA0 65 VCCN 64 ...
Page 3
... VCCN VCCN GND (3_level) VCCN 3QA0 3QA1 GND 3QB0 Pin Description , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination CC RoboClock CY7B993V CY7B994V 9 10 FBKA– FBKA+ FBSEL REFA+ GND REFA– VCCN REFB+ VCCN 2QA0 1F0 2QA1 ...
Page 4
... NOM There are two versions: a low-speed device (CY7B993V) where f ranges from 12 MHz to 100 MHz, and a NOM high-speed device (CY7B994V) that ranges from 24 MHz to 200 MHz. The FS setting for each device is shown in Table 1. The f frequency is seen on “divide-by-one” outputs. For NOM ...
Page 5
... V and Phase Generator. f NOM CO when the output connected undivided. NOM RoboClock CY7B993V CY7B994V Output Skew Function Feed- back Bank1 Bank2 Bank3 Bank4 Bank –4t –4t –8t –8t – ...
Page 6
... When a bank of outputs is disabled to HI-Z state, the respective bank of outputs will go HI-Z immediately. Table 5. DIS[1:4]/FBDIS Pin Functionality OUTPUT_MODE DIS[1:4]/FBDIS HIGH/LOW LOW HIGH HIGH LOW HIGH MID X CY7B993V CY7B994V Output Mode ENABLED HI-Z HOLD-OFF FACTORY TEST Page [+] Feedback ...
Page 7
... MHz is 16 (with 25-pF load and 0-m/s air flow). Typical Safe Operating Zone (25-pF Load, 0-m /s air flow ) 100 Safe Operating Zone Num ber of Outputs at 185 MHz Figure 2. Typical Safe Operating Zone CY7B993V CY7B994V 16 18 Page [+] Feedback ...
Page 8
... Max Max Min. < Min. < Min. < GND IN RoboClock CY7B993V CY7B994V Ambient Temperature V CC ° ° 3.3V ± 10 +70 C ° ° 3.3V ± 10% – +85 C Min. Max. Unit = –30 mA 2.4 – Min. ...
Page 9
... Bank1 and FB Bank configured to run at maximum frequency (f CCI CY7B994V), and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state. 8. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum I load terminated to 50Ω ...
Page 10
... OUTPUT 200 MHz (a) LVTTL AC Test Load 3.3V 2.0V 0.8V GND < (b) TTL Input Test Waveform = 185 MHz 200 MHz. L RoboClock CY7B993V CY7B994V CY7B993/4V-5 Typ. Max. Min. Typ. Max. Unit – 500 – – 700 ps – 200 – ...
Page 11
... CY7B993V-2AIT 250 200 CY7B994V-2AC 250 200 CY7B994V-2ACT 250 200 CY7B994V-2BBC 250 200 CY7B994V-2BBCT 250 200 CY7B994V-2AI 250 200 CY7B994V-2AIT 250 200 CY7B994V-2BBI 250 200 CY7B994V-2BBIT Document #: 38-07127 Rev. *F QFA0 or [1:4]Q[A:B]0 t SKEWPR t PWL QFA1 or [1:4]Q[A:B]1 0.8V t [1:4]QA[0:1] CCJ1-3,4-12 t SKEWBNK [1:4]QB[0: SKEW0,1 Other Q ...
Page 12
... CY7B994V-5ACT 500 200 CY7B994V-5BBC 500 200 CY7B994V-5BBCT 500 200 CY7B994V-5BBI 500 200 CY7B994V-5BBIT 500 200 CY7B994V-5AI 500 200 CY7B994V-5AIT Lead-free 250 100 CY7B993V-2AXC 250 100 CY7B993V-2AXCT 250 100 CY7B993V-2AXI 250 100 CY7B993V-2AXIT 250 200 CY7B994V-2AXC 250 200 CY7B994V-2AXCT 250 ...
Page 13
... Package Diagrams 100-pin Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-07127 Rev. *F RoboClock CY7B993V CY7B994V 51-85048-*B Page [+] Feedback ...
Page 14
... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. RoboClock CY7B993V CY7B994V 51-85107-*B Page [+] Feedback ...
Page 15
... Added three industrial packages HWT Added TTB Features RBI Power-up requirements to operating conditions information RGL Added min. F value of 12 MHz for CY7B993V and 24 MHz for CY7B994V out to switching characteristics table Corrected prop delay limit parameter from (t Output Description paragraph RGL Added clock input frequency (f ...