cy7b9234 Cypress Semiconductor Corporation., cy7b9234 Datasheet - Page 6

• Manufacturer Part Number: cy7b9234
• Description: Smpte Hotlink Transmitter/receiver
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02014 Rev. *A
tolerated is V
preted correctly is V
PECL-TTL Translator
The function of the INB(INB+) input and the SI(INB−) input is
defined by the connections on the SO output pin. If the
PECL/TTL translator function is not required, the SO output is
wired to V
the inputs to become INB± (a differential line-receiver serial-data
input). If the PECL/TTL translator function is required, the SO
output is connected to its normal TTL load (typically one or more
TTL inputs, but no pull-up resistor) and the INB+ input becomes INB
(single-ended ECL 100K, serial data input) and the INB− input
becomes SI (single-ended, ECL 100K status input).
This positive-referenced PECL-to-TTL translator is provided to
eliminate external logic between an PECL fiber-optic interface
module “carrier detect” output and the TTL input in the control
logic. The input threshold is compatible with ECL 100K levels
(+5V referenced). It can also be used as part of the link status
indication logic for wire connected systems.
Clock Synchronization
The Clock Synchronization function is performed by an
embedded phase-locked loop (PLL) that tracks the frequency
of the incoming bit stream and aligns the phase of its internal
bit rate clock to the serial data transitions. This block contains
the logic to transfer the data from the Shifter to the Decode
register once every byte.
transfer is initialized by the Framer logic. CKR is a buffered
output derived from the bit counter used to control the Decode
register and the output register transfers.
Clock output logic is designed so that when reframing causes
the counter sequence to be interrupted, the period and pulse
width of CKR will never be less than normal. Reframing may
stretch the period of CKR by up to 90%, and either CKR Pulse
Width HIGH or Pulse Width LOW may be stretched,
depending on when reframe occurs.
The REFCLK input provides a byte-rate reference frequency
to improve PLL acquisition time and limit unlocked frequency
excursions of the CKR when no data is present at the serial
inputs. The frequency of REFCLK is required to be within
±0.1% of the frequency of the clock that drives the transmitter
CKW pin.
Framer
Framer logic checks the incoming bit-stream for the pattern
that defines the byte boundaries. This combinatorial logic filter
looks for the X3.230 symbol defined as a Special Character
Comma (K28.5). When it is found, the free-running bit counter
in the Clock Synchronization block is synchronously reset to
its initial state, thus framing the data correctly on the correct
byte boundaries.
Random errors that occur in the serial data can corrupt some
data patterns into a bit-pattern identical to a K28.5, and thus
cause an erroneous data-framing error. The RF input prevents
this by inhibiting reframing during times when normal message
data is present. When RF is held LOW, the SMPTE HOTLink
receiver will deserialize the incoming data without trying to
reframe the data to incoming patterns. When RF rises, RDY
will be inhibited until a K28.5 has been detected, after which RDY
will resume its normal function. While RF is HIGH, it is possible that
an error could cause misframing, after which all data will be
corrupted. Likewise, a K28.7 followed by D11.x, D20.x, or an SVS
(C0.7) followed by D11.x will create alias K28.5 characters and
CC
IN
. A sensor circuit will detect this connection and cause
= V
CC
IN
, and the lowest LOW input that can be inter-
= GND+2.0V.
The counter that controls this
cause erroneous framing. These sequences must be avoided while
RF is HIGH.
If RF remains HIGH for greater than 2048 bytes, the framer
converts to double-byte framing, requiring two K28.5
characters aligned on the same byte boundary within 5 bytes
in order to reframe. Double-byte framing greatly reduces the
possibility of erroneously reframing to an aliased K28.5
character.
Shifter
The Shifter accepts serial inputs from the Serial Data inputs
one bit at a time, as clocked by the Clock Synchronization
logic. Data is transferred to the Framer on each bit, and to the
Decode register once per byte.
Decode Register
The Decode register accepts data from the Shifter once per
byte as determined by the logic in the Clock Synchronization
block. It is presented to the Decoder and held until it is trans-
ferred to the output latch.
Decoder
Parallel data is transformed from ANSI-specified X3.230
8B/10B codes back to “raw data” in the Decoder. This block
uses the standard decoder patterns shown in the Valid Data
Characters and Valid Special Character Codes and
Sequences sections of this datasheet. Data patterns are
signaled by a LOW on the SC/D output and Special Character
patterns are signaled by a HIGH on the SC/D output. Unused
patterns or disparity errors are signaled as errors by a HIGH on the
RVS output and by specific Special Character codes.
Output Register
The Output register holds the recovered data (Q
RVS) and aligns it with the recovered byte clock (CKR). This
synchronization insures proper timing to match a FIFO interface or
other logic that requires glitch free and specified output behavior.
Outputs change synchronously with the rising edge of CKR.
In BIST mode, this register becomes the signature pattern
generator and checker by logically converting itself into a
Linear Feedback Shift Register (LFSR) pattern generator.
When enabled, this LFSR will generate a 511-byte sequence
that includes all Data and Special Character codes, including
the explicit violation symbols.
predictable but pseudo-random sequence that can be
matched to an identical LFSR in the Transmitter.
synchronized, it checks each byte in the Decoder with each
byte generated by the LFSR and shows errors at RVS.
Patterns generated by the LFSR are compared after being
buffered to the output pins and then fed back to the compar-
ators, allowing test of the entire receive function.
In BIST mode, the LFSR is initialized by the first occurrence of
the transmitter BIST loop start code D0.0 (D0.0 is sent only
once per BIST loop). Once the BIST loop has been started,
RVS will be HIGH for pattern mismatches between the
received sequence and the internally generated sequence.
Code rule violations or running disparity errors that occur as
part of the BIST loop will not cause an error indication. RDY
will pulse HIGH once per BIST loop and can be used to check test
pattern progress. The receiver BIST generator can be reinitialized
by leaving and re-entering BIST mode.
Test Logic
Test logic includes the initialization and control for the Built-In
Self-Test (BIST) generator, the multiplexer for Test mode clock
distribution, and control logic for the decoder. Test logic is
discussed in more detail in the CY7B9334 SMPTE HOTLink
Receiver Operating Mode Description.
This pattern provides a
CY7B9234
CY7B9334
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, SC/D, and
When
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