cy7b9514v Cypress Semiconductor Corporation., cy7b9514v Datasheet - Page 7

• Manufacturer Part Number: cy7b9514v
• Description: 3.3v Quad Sonet Transceiver
• Manufacturer: Cypress Semiconductor Corporation.

bit times that have passed without a data transition. A bit time
is defined as the period of RCLK±. When 512 bit times have
passed without a data transition on RIN±, LFI will transition
LOW. The receiver will assume that the serial data stream is
invalid, and, instead of allowing the RCLK± frequency to wan-
der in the absence of data, the PLL will lock to the REFCLK*8
frequency. This will insure that RCLK± is as close to the correct
link operating frequency as the REFCLK accuracy. LFI will be
driven HIGH, and the receiver will recover clock and data from
the incoming data stream when the transition detection circuit-
ry determines that at least 64 transitions have been detected
within 256 bit-times. The transition detector is disabled when
MODE1 is held LOW (V
Loop Back Testing
The LVTTL level LOOP pins are used to perform loop-back
testing. When LOOP is asserted (held LOW) the Transmit se-
rial input (TSER±) is used by the respective Receiver PLL for
clock and data recovery. This allows in-system testing to be
performed on each clock and data recovery PLL and transition
detection logic. When a channel is in loop-back mode the state
of the CD pin is ignored. For example, an ATM controller can
present ATM cells to the input of the ATM cell processor and
check to see that these same cells are received from each of
the four channels. When the LOOP input is deasserted (held
HIGH) the Receive PLL is once again connected to the Re-
ceiver serial inputs (RIN±).
The LOOP feature can also be used in applications where
clock and data recovery are to be performed from either of two
data streams from each channel. In these systems the LOOP
pin is used to select whether the TSER± or the RIN± inputs
are used by the Receive PLL for clock and data recovery.
Power-Down Modes
There are several power-down features on the CY7B9514V.
Any of the differential output drivers can be powered down by
either tying both outputs to V
connected where internal pull-up resistors will force these out-
puts to V
in addition to the associated output load current. If the TOUT±
outputs are tied to V
path will be turned off. If the TCLK± outputs are tied to V
left unconnected, the entire Transmit PLL will be powered
down.
For each receive channel, by leaving both the RCLK± and
RSER± outputs unconnected or tied to V
Receive PLL is turned off.
Besides the option of turning off drivers and PLLs selectively,
the PWR_DWN pin can also be used to power down the entire
device. When PWR_DWN pin is at TTL LOW, the Transmit
PLL, transition detection logic and all four Receive PLLs will be
powered down (see application section concerning PECL out-
put loading when PWR_DWN is asserted). When the
PWR_DWN pin is at TTL HIGH, the Transmit PLL, transition
detection logic, and all four Receive PLLs will be enabled.
Applications
The CY7B9514V can be used in Local Area Network ATM ap-
plications. The operating frequency of the CY7B9514V is cen-
tered around the SONET/SDH STS-1 rate of 51.84 MHz and
the SONET/SDH STS-3/STM-1 rate of 155.52 MHz. This de-
CC
. This will save approximately 4 mA per output pair
CC
or left unconnected, the Transmit buffer
SS
).
CC
or by simply leaving them un-
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PRELIMINARY
, the corresponding
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or
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vice can also be used in data mover and Local Area Network
(LAN) applications that operate at these frequencies.
The CY7B9514V can provide clock and data recovery as well
as output buffering for physical layer protocol engines such as
the SONET/SDH and ATM processing application shown in
Figure 1.
Figure 1 shows the CY7B9514V in an ATM system that uses
the IgT WAC-413 device. The CY7B9514V will recover clock
and data from the input serial data streams and pass them to
the WAC-413. The WAC-413 device will perform serial to par-
allel conversion on each channel, SONET/SDH overhead pro-
cessing, and ATM cell processing and then pass ATM cells to
an ATM packet reassembly engine. On the Transmit side, a
segmentation engine will divide long packets of data such as
Ethernet packets into 53 byte cells and pass them to each of
the channels of the WAC-413. The WAC-413 device will then
perform ATM cell processing, such as header generation,
SONET/SDH overhead processing, and parallel to serial con-
version on each channel. These serial data streams will then
be passed to the CY7B9514V, which will buffer these data
streams and pass them along to the transmission media.
The CY7B9514V provides the necessary clock and data re-
covery function to the WAC-413. These differential PECL clock
and data signals interface directly with the RS_SER_DATA±
and RS_SER_CLK± inputs of the WAC-413 device as shown
in Figure 1 . In addition, the CY7B9514V provides transmit data
output buffering for direct drive of cable transmission media.
The CY7B9514V has two local reference clock inputs. An in-
ternal mux controls which input clock is used as the reference.
Changing from one input to the other will happen smoothly
without glitch on REFOUT. Therefore, a low-cost crystal oscil-
lator can drive one input, and a clock from another external
clock source, e.g., a distributed clock from a central clock
board, can drive the other clock input. Another application of
the two clock inputs is feeding a 19.44-MHz clock to one input
and a 6.48-MHz to the other clock input, so now the
CY7B9514V can operate at both STS-1/OC-1 rate as well as
STS-3/OC-3/STM-1 rate by configuring the MODE0 pin and
REFSEL pin to the appropriate state. Lastly, the CY7B9514V
provides a bit rate reference clock to the WAC-413 transmitter
by multiplying one of the two local reference clocks by eight.
Utilized PECL outputs must be terminated by external resis-
tors at the end of the connected transmission line. Figure 2
shows an example of terminating a 50 transmission line con-
nected to a pair of PECL outputs.
CY7B9514V offers a Power-Down feature. When the
PWR_DWN input is asserted (to a TTL LOW), the Transmit
PLL, transition detection logic, and Receive PLLs will power
down. When this power-down feature is used, a power-down
control circuit shall be implemented at each PECL output ter-
mination as shown in Figure 3 . Each power-down control block
will connect the terminating resistors to ground in normal op-
erating mode. The pass gate, shown in Figure 3 , must be able
to sink at least 25 mA when turned on. It also provides a low
resistance path to ground. In power-down mode, the pow-
er-down control circuit will allow the terminating resistors to
pull both outputs to V
The power-down control logic should consume minimal power
when in power-down mode (i.e., PWR_DWN asserted). A
CMOS device is suitable to implement the power down control
logic. CYBUS3384 is a good candidate for this application.
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.
CY7B9514V