adclk948 Analog Devices, Inc., adclk948 Datasheet - Page 6

• Manufacturer Part Number: adclk948
• Description: Two Selectable Inputs, 8 Lvpecl Outputs, Sige Clock Fanout Buffer
• Manufacturer: Analog Devices, Inc.

ADCLK948
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10, 15, 16, 25, 26, 31
11, 12
13, 14
17, 18
19, 20
21, 22
23, 24
27, 28
29, 30
32
(33)
Mnemonic
CLK0
CLK0
V
V
CLK1
CLK1
V
V
NC
V
Q7, Q7
Q6, Q6
Q5, Q5
Q4, Q4
Q3, Q3
Q2, Q2
Q1, Q1
Q0, Q0
IN_SEL
EPAD
REF
T
T
REF
CC
1
0
1
0
Description
Differential Input (Positive) 0.
Differential Input (Negative) 0.
Reference Voltage. Reference voltage for biasing ac-coupled CLK0 and CLK0 inputs.
Center Tap. Center tap of a 100 Ω input resistor for CLK0 and CLK0 inputs.
Differential Input (Positive) 1.
Differential Input (Negative) 1.
Center Tap. Center tap of a 100 Ω input resistor for CLK1 and CLK1 inputs.
Reference Voltage. Reference voltage for biasing ac-coupled CLK1 and CLK1 inputs.
No Connection.
Positive Supply Pin.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Differential LVPECL Outputs.
Input Select. Logic 0 selects CLK0 and CLK0 inputs. Logic 1 selects CLK1 and CLK1 inputs.
EPAD must be connected to V
V
V
NOTES
1. NC = NO CONNECT.
2. EPAD MUST BE SOLDERED TO V
CLK0
CLK0
CLK1
CLK1
REF
REF
V
V
T
T
0
0
1
1
1
2
3
4
5
6
7
8
Figure 2. Pin Configuration
ADCLK948
(Not to Scale)
PIN 1
INDICATOR
TOP VIEW
Rev. 0 | Page 6 of 12
EE
.
EE
24 Q2
23 Q2
22 Q3
21 Q3
20 Q4
19 Q4
18 Q5
17 Q5
POWER PLANE.