lv8104v Sanyo Semiconductor Corporation, lv8104v Datasheet - Page 16

• Manufacturer Part Number: lv8104v
• Description: Three-phase Brushless Motor Predriver
• Manufacturer: Sanyo Semiconductor Corporation

Description of LV8104V
1. Speed control circuit
2. VCO circuit
3. Output drive circuit
4. Speed lock range
5. Hall input signal
6. Current limiter circuit
7. S/S switching circuit
This IC controls the speed with a combination of the speed discriminator circuit and the PLL circuit. Therefore, when a
motor that has large load variation is used, it is possible to prevent the rotation variation as compared with the speed
control method only the speed discriminator. The speed discriminator circuit and the PLL circuit outputs an error signal
once every one FG period. The FG servo frequency signal (f FG ) is controlled to have the equal frequency with the
clock signal (f CLK ) which is input through the CLK pin.
This IC has the VCO circuit to generate the reference signal of the speed discriminator circuit. The reference signal
frequency is calculated as follows.
The components connected to the R, C and FIL pins must be connected to the GND1 pin (pin 3) with a line that is as
short as possible to reduce influence of noise.
This IC can be used to implement both upper and lower output N channel power FET drive circuit using a built-in
charge pump circuit. The upper side gate voltage is V CC +9V. The lower side gate voltage is VREG(5.6V).
The PWM switching is performed on the UL, VL and WL pins. Therefore, it is performed on the lower output N
channel power FET. The driving force of the motor is adjusted by changing the duty that the lower output N channel
power FET is on. The PWM frequency is determined with 20kHz (typical) in the IC.
When the PWM switching of the lower output N channel power FET is off, the upper output N channel power FET is
turned on (Synchronous rectification). Therefore, it is possible to reduce the temperature increase of the upper output N
channel power FET.The off-time of the synchronous rectification is determined in the IC and varies from 1.7μs to
3.7μs.
The speed lock range is less than ±6.25% of the fixes speed. When the motor speed is in the lock range, the LD pin (an
open collector output) goes low. If the motor speed goes out of the lock range, the PWM output on-duty is adjusted
according to the speed error to control the motor speed to be within the lock range.
The input amplitude of 100mVp-p or more (differential) is desirable in the Hall sensor inputs. The closer the input
wave-form is to a square wave, the required input amplitude is lower. Inversely, the closer the input waveform is to a
triangular wave, the higher input amplitude is required. Also, note that the input DC voltage must be set to be within the
common-mode input voltage range.
If a Hall sensor IC is used to provide the Hall inputs, those signals can be input to one side (either the + or - side) of the
Hall sensor signal inputs as 0 to VREG level signals if the other side is held fixed at a voltage within the common-mode
input voltage range that applies when the Hall sensors are used.
If noise on the Hall inputs is a problem, that noise must be excluded by inserting capacitors across the inputs. Those
capacitors must be located as close as possible to the input pins. When the Hall inputs for all three phases are in the
same state, all the outputs will be in the off state.
The current limiter circuit limits the (peak) current at the value I = V RF /Rf (V RF = 0.25V (typical), Rf : current
detection resistor). The current limitation operation consists of reducing the PWM output on-duty to suppress the
current.
High accuracy detection can be achieved by connecting the RF and RFGND pins lines near at the ends of the current
detection resistor (Rf).
When the S/S pin is set to the low level, S/S switching circuit is the start mode. Inversely, when the S/S pin is set to the
high level or open, S/S switching circuit is the stop mode. This IC will be in the power save state of decreasing the
supply current at the stop mode. The bias current to most of the circuit in the IC is cut off in the power save state. The
operating circuit in the power save state are limited to the S/S switching circuit , the 5V constant voltage output, FG
amplifier and FG amplifier Schmitt output. The other circuit do not operate. The upper side output transistors for all
phases (the UH, VH and WH side) and the lower side output transistors for all phases (the UL, VL and WL side) are
turned off in the power save state.
f FG = f CLK
f VCO = f CLK × 512
f VCO : Reference signal frequency, f CLK : Clock signal frequency
LV8104V
No.A1677-16/19