nb3n3011 ON Semiconductor, nb3n3011 Datasheet - Page 5

• Manufacturer Part Number: nb3n3011
• Description: 3.3 V 100 Mhz / 106.25 Mhz Pureedge Clock Generator With Lvpecl Differential Output
• Manufacturer: ON Semiconductor

Power Supply Filtering
such, it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is
naturally susceptible to random noise, especially if this noise
is seen on the power supply pins. The NB3N3011 also
generates sub−nanosecond output edge rates, and therefore,
a good power supply bypassing scheme is a must.
digital circuitry (V
simplest form of noise isolation is a power supply filter on
the V
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL.
the high switching noise of the digital outputs from the
relatively sensitive internal analog phase−locked loop. The
power supply filter and bypass schemes discussed in this
section should be adequate to eliminate power supply
noise−related problems in most designs.
Crystal Oscillator Input Interface
minimize system implementation costs. The oscillator
circuit is a parallel resonant circuit and thus, for optimum
performance, a parallel resonant crystal should be used.
inputs, the user is advised to mount the crystal as close to the
NB3N3011 as possible to avoid any board level parasitics.
Surface mount crystals are recommended, but not required.
An example of LVPECL termination is shown in this
schematic. Additional LVPECL termination approaches are
shown in the AND8020 Application Note. In this example,
an 18 pF parallel resonant 26.5625MHz crystal is used for
The NB3N3011 is a mixed analog/digital product, and as
The NB3N3011 provides separate power supplies for the
Figure 8 illustrates a typical power supply filter scheme.
The purpose of this design technique is to try and isolate
The NB3N3011 features an integrated crystal oscillator to
As the oscillator is somewhat sensitive to loading on its
Figure 10 shows a schematic example of the NB3N3011.
33 pF
C2
CCA
V
CC
pin.
R2
10
18 pF
10 mF
C3
CC
) and the internal PLL (V
C1
27 pF
X1
0.01 mF
C4
V
CCA
Figure 10. Typical Application Schematic
1
2
3
4
U1
APPLICATION INFORMATION
V
V
X
X
APPLICATION SCHEMATIC
CCA
EE
OUT
IN
CCA
V
CC
http://onsemi.com
). The
= 3.3 V
V
NC
5
CC
Q
Q
associated load capacitors. The capacitor values shown were
determined using a 26.5625 MHz, 18 pF parallel resonant
crystal and were chosen to minimize the ppm error.
Capacitor values can be adjusted slightly for different board
layouts to optimize accuracy.
generating 106.25 MHz output frequency. The C1 = 27 pF
and C2 = 33 pF are recommended for frequency accuracy.
For different board layout, the C1 and C2 values may be
slightly adjusted for optimizing frequency accuracy.
8
7
6
5
Figure 9 illustrates a parallel resonant crystal with its
18 pF
V
CC
Parallel Crystal
C5
Figure 8. Power Supply Filtering
Figure 9. Crystal Input Interface
0.1 m
Q
Q
V
V
CCA
CC
Z
Z
X1
O
O
= 50 W
= 50 W
0.01 mF
82.5
133
0.01 mF
R3
R4
C1
33 pF
C2
27 pF
V
3.3 V
CC
10 W
10 mF
R5
133
R6
82.5
X
X
OUT
IN
+
−