max9130extt Maxim Integrated Products, Inc., max9130extt Datasheet - Page 7

• Manufacturer Part Number: max9130extt
• Description: Max9130 Single 500mbps Lvds Line Receiver In Sc70
• Manufacturer: Maxim Integrated Products, Inc.

Input trace characteristics affect the performance of the
MAX9130. Use controlled-impedance PC board traces,
typically 100Ω. Match the termination resistor to this
characteristic impedance.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Input differential signals should be routed close to each
other to cancel their external magnetic field. Maintain a
constant distance between the differential traces to
avoid discontinuities in differential impedance. Minimize
the number of vias to further prevent impedance dis-
continuities.
Transmission media should typically have a controlled
differential impedance of 100Ω. Use cables and con-
nectors that have matched differential impedance to
minimize impedance discontinuities.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by the LVDS receiver.
The MAX9130 requires an external termination resistor.
The termination resistor should match the differential
impedance of the transmission line. Termination resis-
tance is typically 100Ω but may range between 90Ω to
132Ω, depending on the characteristic impedance of
the transmission medium.
When using the MAX9130, minimize the distance
between the input termination resistor and the MAX9130
receiver inputs. Use 1% surface-mount resistors.
For LVDS applications, use a four-layer PC board that
provides separate layers for power, ground, and
input/output signals is recommended. Keep the LVDS
input signals away from the output LVCMOS/LVTTL sig-
nal to prevent coupling (Figure 4). To minimize
crosstalk, do not run the output in parallel with the
inputs.
Single 500Mbps LVDS Line Receiver in SC70
_______________________________________________________________________________________
Cables and Connectors
Differential Traces
Board Layout
Termination
TRANSISTOR COUNT: 201
PROCESS: CMOS
Figure 3. Propagation Delay and Transition Time Waveforms
Figure 4. Board Layout
V
V
V
OUT
IN+
IN-
COMMON-MODE VOLTAGE: V
DIFFERENTIAL INPUT VOLTAGE: V
U1: MAX9130
R1, C1 ARE 0402 TYPE
C1
0.01µF
20%
t
50%
PLHD
V
ID
t
= 0
TLH
R1
CM
80%
= (V
ID
(LVTTL/LVCMOS OUTPUT)
GND
V
= (V
IN-
CC
IN+
IN+
+ V
V
ID
) - (V
IN-
Chip Information
) / 2
IN-
)
U1
80%
INPUTS)
t
(LVDS
PHLD
GND
V
OUT
ID
IN+
t
THL
= 0
50%
20%
V
V
OH
OL
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