max9205eait Maxim Integrated Products, Inc., max9205eait Datasheet - Page 5

• Manufacturer Part Number: max9205eait
• Description: 10-bit, Bus Lvds Serializers
• Manufacturer: Maxim Integrated Products, Inc.

The MAX9205/MAX9207 are 10-bit serializers designed
to transmit data over balanced media that may be a
standard twisted-pair cable or PC board traces at
160Mbps to 660Mbps. The interface may be double-
terminated point-to-point or a heavily loaded multipoint
bus. The characteristic impedance of the media and
connected devices can range from 100Ω for a point-to-
point interface to 54Ω for a heavily loaded multipoint
bus. A double-terminated point-to-point interface uses
a 100Ω-termination resistor at each end of the inter-
face, resulting in a load of 50Ω. A heavily loaded multi-
point bus requires a termination as low as 54Ω at each
end of the bus, resulting in a termination load of 27Ω.
The serializer requires a deserializer such as the
MAX9206/MAX9208 for a complete data transmission
application.
18, 20,
15, 16
17, 26
23, 25
27, 28
3–12
PIN
1, 2
13
14
19
21
22
24
TCLK_R/F
SYNC 1,
IN0–IN9
PWRDN
SYNC 2
NAME
DGND
AGND
OUT+
DV
TCLK
AV
OUT-
_______________________________________________________________________________________
EN
CC
CC
Detailed Description
LVCMOS/LVTTL Logic Inputs. The two SYNC pins are ORed. When at least one of the two pins
are asserted high for at least six cycles of TCLK, the serializer initiates a transmission of 1024
SYNC patterns. If held high after 1024 SYNC patterns have been transmitted, SYNC patterns
continue to be sent until the SYNC pin is asserted low. Toggling a SYNC pin after six TCLK cycles
high and before 1024 SYNC patterns have been transmitted does not affect the output of the 1024
SYNC patterns.
LVCMOS/LVTTL Data Inputs. Data is loaded into a 10-bit latch by the selected TCLK edge.
LVCMOS/LVTTL Logic Input. High selects a TCLK rising-edge data strobe. Low selects a TCLK
falling-edge data strobe.
LVCMOS/LVTTL Reference Clock Input. The MAX9205 accepts a 16MHz to 40MHz clock. The
MAX9207 accepts a 40MHz to 66MHz clock. TCLK provides a frequency reference to the PLL and
strobes parallel data into the input latch.
Digital Circuit Ground. Connect to ground plane.
Analog Circuit Power Supply (Includes PLL). Bypass AV
0.001µF capacitor. Place the 0.001µF capacitor closest to AV
Analog Circuit Ground. Connect to ground plane.
LVCMOS/LVTTL Logic Input. High enables serial data output. Low puts the bus LVDS output into
high impedance.
Inverting Bus LVDS Differential Output
Noninverting Bus LVDS Differential Output
LVCMOS/LVTTL Logic Input. Low puts the device into power-down mode and the output into high
impedance.
Digital Circuit Power Supply. Bypass DV
capacitor. Place the 0.001µF capacitor closest to DV
10-Bit Bus LVDS Serializers
A high-state start bit and a low-state stop bit, added
internally, frame the 10-bit parallel input data and
ensure a transition in the serial data stream. Therefore,
12 serial bits are transmitted for each 10-bit parallel
input. The MAX9205 accepts a 16MHz to 40MHz refer-
ence clock, producing a serial data rate of 192Mbps
(12 bits x 16MHz) to 480Mbps (12 bits x 40MHz). The
MAX9207 accepts a 40MHz to 66MHz reference clock,
producing 480Mbps to 792Mbps. However, since only
10 bits are from input data, the actual throughput is 10
times the TCLK frequency.
To transmit data, the serializers sequence through
three modes: initialization mode, synchronization mode,
and data transmission mode.
CC
to ground with a 0.1µF capacitor and a 0.001µF
FUNCTION
CC
.
CC
to ground with a 0.1µF capacitor and a
CC
.
Pin Description
5