max9320euat Maxim Integrated Products, Inc., max9320euat Datasheet - Page 7

• Manufacturer Part Number: max9320euat
• Description: 1 2 Differential Lvpecl/lvecl/hstl Clock And Data Drivers
• Manufacturer: Maxim Integrated Products, Inc.

Figure 1. Differential Transition Time and Propagation Delay
Timing Diagram
The MAX9320/MAX9320A low-skew, 1-to-2 differential
drivers are designed for clock and data distribution. For
interfacing to differential HSTL and LVPECL signals,
these devices operate over a +2.25V to +3.8V supply
range, allowing high-performance clock and data distri-
bution in systems with a nominal +2.5V or +3.3V sup-
ply. For differential LVECL operation, these devices
operate from a -2.25V to -3.8V supply.
The maximum magnitude of the differential input from D
to D is V
also applies to the difference between any reference
voltage input and a single-ended input.
The differential inputs have bias resistors that drive the
outputs to a differential low when the inputs are open.
The inverting input, D, is biased with a 60kΩ pullup to
V
input, D, is biased with a 100kΩ pulldown to V
Specifications for the high and low voltages of the dif-
ferential input (V
voltage (V
be higher than V
Output levels are referenced to V
ered LVPECL or LVECL, depending on the level of the
V
and V
The outputs are LVECL when V
and V
(Q_) - (Q_)
CC
CC
Q_
D
D
Q
and a 100kΩ pulldown to V
supply. With V
EE
EE
is connected to a negative supply.
CC
connected to GND, the outputs are LVPECL.
IHD
- V
- V
t
EE
PLHD
20%
IHD
IHD
ILD
_______________________________________________________________________________________
or 3.0V, whichever is less. This limit
).
) apply simultaneously (V
CC
and V
t
R
Detailed Description
connected to a positive supply
0 (DIFFERENTIAL)
80%
V
IHD -
ILD
V
1:2 Differential LVPECL/LVECL/HSTL
ILD
) and the differential input
CC
V
OH -
EE
is connected to GND
V
CC
OL
t
PHLD
80%
. The noninverting
and are consid-
t
F
0 (DIFFERENTIAL)
20%
ILD
Outputs
EE
Inputs
.
cannot
V
V
V
V
IHD
ILD
OH
OL
Clock and Data Drivers
A single-ended input of ±100mV around a reference
voltage or a differential input of at least ±100mV switch-
es the outputs to the V
the DC Electrical Characteristics table.
Bypass V
ceramic 0.1µF and 0.01µF capacitors in parallel as
close to the device as possible, with the 0.01µF value
capacitor closest to the device. Use multiple parallel
vias for low inductance.
Input and output trace characteristics affect the perfor-
mance of the MAX9320/MAX9320A. Connect each
signal of a differential input or output to a 50Ω charac-
teristic impedance trace. Minimize the number of vias
to prevent impedance discontinuities. Reduce reflec-
tions by maintaining the 50Ω characteristic impedance
through connectors and across cables. Reduce skew
within a differential pair by matching the electrical
length of the traces.
The exposed-pad (EP) SO package can be soldered to
the PC board for enhanced thermal performance. If the
EP is not soldered to the PC board, the thermal resis-
tance is the same as the regular SO package. The EP
is connected to the chip V
pad does not touch signal lines or other supplies.
Contact the Maxim Packaging department for guide-
lines on the use of EP packages.
Terminate outputs through 50Ω to V
equivalent Thevenin termination. Terminate both out-
puts and use the same termination on each for the low-
est output-to-output skew. When a single-ended signal
is taken from a differential output, terminate both out-
puts. For example, if Q0 is used as a single-ended out-
put, terminate both Q0 and Q0.
TRANSISTOR COUNT: 182
CC
to V
Applications Information
EE
with high-frequency surface-mount
OH
EE
and V
Chip Information
Output Termination
supply. Be sure that the
Supply Bypassing
OL
CC
levels specified in
- 2V or use an
Traces
7