max9325eqit Maxim Integrated Products, Inc., max9325eqit Datasheet
max9325eqit
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max9325eqit Summary of contents
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Rev 3; 11/04 2:8 Differential LVPECL/LVECL/HSTL Clock and General Description The MAX9325 low-skew, 2:8 differential driver features extremely low output-to-output skew (50ps max) and part-to-part skew (225ps max). These features make the device ideal for clock and data distribution ...
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Differential LVPECL/LVECL/HSTL Clock and Data Driver ABSOLUTE MAXIMUM RATINGS ...............................................................-0.3V to +4. CLK_, CLK_SEL Inputs (CLK_, ......-0. CLK_ to CLK_ .....................................................................±3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA V ...
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Differential LVPECL/LVECL/HSTL Clock and DC ELECTRICAL CHARACTERISTICS (continued) (( 2.375V to 3.8V 50Ω ± (Notes 1–4) PARAMETER SYMBOL CONDITIONS Differential Input V Figure 1 ILD Low Voltage (V ...
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Differential LVPECL/LVECL/HSTL Clock and Data Driver AC ELECTRICAL CHARACTERISTICS—PLCC Package (( 2.375V to 3.8V 50Ω ± are 3.3V ...
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Differential LVPECL/LVECL/HSTL Clock and AC ELECTRICAL CHARACTERISTICS—QFN Package (( 2.375V to 3.8V 50Ω ± are 3.3V 1V), V ...
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Differential LVPECL/LVECL/HSTL Clock and Data Driver (PLCC package, typical values are at (V 500MHz, input transition time = 125ps (20% to 80%).) SUPPLY CURRENT (I vs. TEMPERATURE -40 -15 10 TEMPERATURE (°C) ...
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Differential LVPECL/LVECL/HSTL Clock and PIN NAME PLCC QFN 11, 18 CLK0 CLK1 CLK1 N. ...
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Differential LVPECL/LVECL/HSTL Clock and Data Driver IHD ILD IHD ILD V EE DIFFERENTIAL INPUT VOLTAGE DEFINITION Figure 1. Input Voltage Definitions CLK CLK Q_ Q_ DIFFERENTIAL OUTPUT WAVEFORM ...
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Differential LVPECL/LVECL/HSTL Clock and CLK_ WHEN CLK_ = CLK_ WHEN CLK_ = Figure 3. Single-Ended Input (CLK_, CLK_) to Output (Q_, Q_) Delay Timing Diagram Detailed Description The MAX9325 low-skew, 2:8 differential ...
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Differential LVPECL/LVECL/HSTL Clock and Data Driver ferential input is configured for single-ended operation by connecting the on-chip reference voltage, V unused complementary input as a reference. For exam- ple, the differential CLK0, CLK0 input is converted to a noninverting, ...
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Differential LVPECL/LVECL/HSTL Clock and (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages NOTES: ...
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Differential LVPECL/LVECL/HSTL Clock and Data Driver (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other ...