max9389etj-t Maxim Integrated Products, Inc., max9389etj-t Datasheet - Page 8

• Manufacturer Part Number: max9389etj-t
• Description: Max9389 Differential 8 1 Ecl/pecl Multiplexer With Dual Output Buffers
• Manufacturer: Maxim Integrated Products, Inc.

In single-ended operation, ensure that the supply volt-
age (V
minimum level must be at least (V
for proper operation. The reference voltage V
be at least (V
level input when a single-ended input swings below it.
The minimum V
1.525V). Substituting the minimum V
= V
of 2.725V. Rounding up to standard supplies gives the
recommended single-ended operating supply ranges
(V
When using the V
0.01µF ceramic capacitor to V
used, leave it unconnected. The V
source or sink a total of 0.5mA (shared between V
and V
Terminate each output with a 50Ω to V
equivalent Thevenin termination. Terminate each Q_
and Q_ output with identical termination for minimal dis-
tortion. When a single-ended signal is taken from the
differential output, terminate both Q_ and Q_.
Ensure that the output current does not exceed the cur-
rent limits specified in the Absolute Maximum Ratings
table. Under all operating conditions, the device’s total
thermal limits should not be exceeded.
Bypass each V
mount ceramic 0.1µF and 0.01µF capacitors. For PECL,
bypass each V
V
sible with the 0.01µF capacitor closest to the device pins.
Use multiple vias when connecting the bypass capacitors
to ground. When using the V
puts, bypass each one with a 0.01µF ceramic capacitor
to V
used, they can be left open.
Differential 8:1 ECL/PECL Multiplexer with
Dual Output Buffers
8
CC
CC
EE
_______________________________________________________________________________________
. Place the capacitors as close to the device as pos-
CC
- V
BB2
+ 1.2V) results in a minimum supply (V
CC
. If the V
EE
), which is sufficient to drive eight inputs.
-V
) of 3.0V to 5.5V.
EE
EE
) is greater than 2.725V. The input high
CC
CC
Applications Information
BB1
BB
+ 1.2V) because it becomes the high-
BB
to V
to V
output for the MAX9389 is (V
or V
reference output, bypass it with a
EE
EE
. For ECL, bypass each V
BB2
with high-frequency surface-
BB1
reference outputs are not
Output Termination
CC
Supply Bypassing
or V
. If V
EE
BB
BB
BB2
+ 1.2V) or higher
CC
BB
output for (V
reference can
- 2V or use an
reference out-
is not being
CC
BB
- V
EE
must
CC
BB1
EE
BB
to
-
)
Circuit board trace layout is very important to maintain the
signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reducing
signal reflections and skew, and increasing common-
mode noise immunity.
Signal reflections are caused by discontinuities in the
50Ω characteristic impedance of the traces. Avoid
discontinuities by maintaining the distance between
differential traces, not using sharp corners or using
vias. Maintaining distance between the traces also
increases common-mode noise immunity. Reducing
signal skew is accomplished by matching the electrical
length of the differential traces.
TRANSISTOR COUNT: 716
PROCESS: Bipolar
Pin Configurations (continued)
NOTE: V
TO THE UNDERSIDE
METAL SLUG.
TOP VIEW
V
V
V
V
BB2
BB1
D0
D0
D1
D1
CC
CC
EE
IS CONNECTED
1
2
3
4
5
6
7
8
THIN QFN
MAX9389
Chip Information
24
23
22
21
20
19
18
17
SEL1
SEL0
V
D7
D7
D6
D6
V
CC
EE
Traces