max9371eua-t Maxim Integrated Products, Inc., max9371eua-t Datasheet - Page 5

• Manufacturer Part Number: max9371eua-t
• Description: Lvttl/ttl-to-differential Lvpecl/pecl Translators
• Manufacturer: Maxim Integrated Products, Inc.

The MAX9370/MAX9371/MAX9372 LVTTL/TTL-to-differ-
ential LVPECL/PECL translators are designed for high-
speed communication signal and clock driver
applications. The MAX9370/MAX9372 are dual LVTTL-
to-LVPECL/PECL translators that operate in excess of
1GHz. The MAX9371 is a single translator. The
MAX9370/MAX9371 operate over a wide 3.0V to 5.25V
supply range, allowing high-performance clock or data
distribution in systems with a nominal 3.3V or 5.0V sup-
ply. The MAX9372 is optimized for 3.0V to 3.6V opera-
tion. These devices feature low 270ps propagation
delay and 40ps peak-to-peak deterministic jitter.
µMAX
1, 4, 6
µMAX
SO
SO
2
3
5
7
8
1
2
3
4
5
6
7
8
PIN
PIN
SOT23
SOT23
4, 5, 8
7
6
2
3
1
8
7
6
5
2
4
3
1
_______________________________________________________________________________________
NAME
NAME
GND
GND
N.C.
V
V
Q0
Q0
Q1
Q1
LVTTL/TTL-to-Differential LVPECL/PECL
D1
D0
Q
Q
D
CC
CC
Detailed Description
No Connection. No internal connection.
Noninverting Differential LVPECL/PECL Output. Typically terminate with 50 resistor to V
Inverting Differential LVPECL/PECL Output. Typically terminate with 50 resistor to V
Ground. Provide a low-impedance connection to ground plane.
LVTTL/TTL Input
Positive Supply Voltage. Bypass V
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
Noninverting Differential LVPECL/PECL Output 0. Typically terminate with 50 resistor to V
Inverting Differential LVPECL/PECL Output 0. Typically terminate with 50 resistor to V
Noninverting Differential LVPECL/PECL Output 1. Typically terminate with 50 resistor to V
Inverting Differential LVPECL/PECL Output 1. Typically terminate with 50 resistor to V
Ground. Provide a low-impedance connection to ground plane.
LVTTL/TTL Input 1. LVTTL/TTL input for translator corresponding to output Q1 and Q1.
LVTTL/TTL Input 0. LVTTL/TTL input for translator corresponding to output Q0 and Q0.
Positive Supply Voltage. Bypass V
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
Pin Description for the MAX9370/MAX9372
CC
CC
to GND with 0.1µF and 0.01µF ceramic capacitors. Place the
to GND with 0.1µF and 0.01µF ceramic capacitors. Place the
The MAX9370/MAX9371/MAX9372 inputs accept stan-
dard LVTTL/TTL levels. The input has pullup circuitry that
drives the outputs to a differential high if the inputs are
open. The outputs are differential LVPECL/PECL levels.
Terminate outputs with 50
alent Thevenin termination. Use the same terminate on
each output for the lowest output-to-output skew. When a
single-ended signal is taken from a differential output,
terminate both outputs. For example, if Q is used as a
single-ended output, terminate both Q and Q.
Pin Description for the MAX9371
FUNCTION
FUNCTION
Applications Information
Translators
to V
Output Termination
Inputs and Outputs
CC
- 2V or use an equiv-
CC
CC
CC
- 2V.
CC
- 2V.
- 2V.
CC
CC
- 2V.
- 2V.
- 2V.
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